Subrata Banik has uploaded this change for review.
util/ifdtool: Use Pch Strap Length(PSL) to uniquely identify IFDv2 chipsets
This patch fixes issue reported with CB:44815, where ifdtool is unable
to identify Lynx Point and Alder Lake chipsets. Hence, this patch make
below changes to fix this issue proper:
1. Refactor chipset name macros to identify chipets more accurately,
example: CNP, ICP and JSL chipsets macros are not seperated with proper
naming.
2. Use offset FLMAP1 bit 24:31, called PSL (PCH Strap Lenth) to uniquely
identify the chipsets without any additional logic.
Note: The same offset was known as ISL in IFDv1 hence, used the backward
compatibility without additional complexity.
+---------+-----------+
| Chipset | PSL Value |
+---------+-----------+
| APL/GLK | 0x13 |
+---------+-----------+
| JSL | 0x2a |
+---------+-----------+
| CNP | 0x45 |
+---------+-----------+
| TGP/ADP | 0x46 |
+---------+-----------+
| ICP | 0x4a |
+---------+-----------+
3. Remove unused argument 1 from guess_ich_chipset() function.
BUG=b:153888802
TEST=Able to dump FD contains correctly without specifying platform
quirks on Brya Platform.
> ifdtool -d coreboot.rom
Without this CL :
PCH Revision: 100/200 series Sunrise Point
With this CL :
PCH Revision: 500 series Tiger Point/ 600 series Alder Point
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I25f69ce775454409974056d8326c02e29038ec8a
---
M util/ifdtool/ifdtool.c
M util/ifdtool/ifdtool.h
2 files changed, 37 insertions(+), 26 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/54305/1
diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c
index 7dbed66..c0c8812 100644
--- a/util/ifdtool/ifdtool.c
+++ b/util/ifdtool/ifdtool.c
@@ -69,9 +69,11 @@
"8 series Wellsburg",
"9 series Wildcat Point",
"9 series Wildcat Point LP",
- "Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx",
+ "Apollo Lake/Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx",
+ "Jasper Lake: N6xxx, N51xx, N45xx",
"100/200 series Sunrise Point",
- "300 series Cannon Point/ 400 series Ice Point",
+ "300 series Cannon Point",
+ "400 series Ice Point",
"500 series Tiger Point/ 600 series Alder Point",
"C620 series Lewisburg",
NULL
@@ -165,29 +167,26 @@
return PTR_IN_RANGE(fmsba, image, size) ? fmsba : NULL;
}
-static enum ich_chipset guess_ifd_2_chipset(const fpsba_t *fpsba)
+static enum ich_chipset guess_ifd_2_chipset(const uint32_t psl)
{
- uint32_t pchstrp_22 = fpsba->pchstrp[22];
- uint32_t pchstrp_23 = fpsba->pchstrp[23];
-
- /* Offset 0x5B is the last PCH descriptor record */
- if (pchstrp_23 == 0xFFFFFFFF)
- return CHIPSET_N_J_SERIES;
-
- /* Offset 0x58 is PCH descriptor record is reserved */
- if (pchstrp_22 == 0x0)
- return CHIPSET_300_400_SERIES_CANNON_ICE_POINT;
-
- /* Offset 0x58 bit [2:0] is reserved 0x4 and 0x5a bit [7:0] is reserved 0x58 */
- if (((pchstrp_22 & 0x07) == 0x4) &&
- ((pchstrp_22 & 0xFF0000) >> 16 == 0x58))
+ switch (psl) {
+ case PSL_APL_GLK:
+ return CHIPSET_N_J_SERIES_APOLLO_GEMINI_LAKE;
+ case PSL_JSL:
+ return CHIPSET_N_SERIES_JASPER_LAKE;
+ case PSL_CNP:
+ return CHIPSET_300_SERIES_CANNON_POINT;
+ case PSL_TGP_ADP:
return CHIPSET_500_600_SERIES_TIGER_ALDER_POINT;
-
- return CHIPSET_PCH_UNKNOWN;
+ case PSL_ICP:
+ return CHIPSET_400_SERIES_ICE_POINT;
+ default:
+ return CHIPSET_PCH_UNKNOWN;
+ }
}
/* port from flashrom */
-static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb, const fpsba_t *fpsba)
+static enum ich_chipset guess_ich_chipset(const fdbar_t *fdb)
{
uint32_t iccriba = (fdb->flmap2 >> 16) & 0xff;
uint32_t msl = (fdb->flmap2 >> 8) & 0xff;
@@ -196,7 +195,7 @@
int temp_chipset;
/* Check for IFD2 chipset type */
- temp_chipset = guess_ifd_2_chipset(fpsba);
+ temp_chipset = guess_ifd_2_chipset(isl);
if (temp_chipset != CHIPSET_PCH_UNKNOWN)
return temp_chipset;
@@ -264,11 +263,10 @@
int read_freq;
const fcba_t *fcba = find_fcba(image, size);
const fdbar_t *fdb = find_fd(image, size);
- const fpsba_t *fpsba = find_fpsba(image, size);
- if (!fcba || !fdb || !fpsba)
+ if (!fcba || !fdb)
exit(EXIT_FAILURE);
- chipset = guess_ich_chipset(fdb, fpsba);
+ chipset = guess_ich_chipset(fdb);
/* TODO: port ifd_version and max_regions
* against guess_ich_chipset()
*/
diff --git a/util/ifdtool/ifdtool.h b/util/ifdtool/ifdtool.h
index ced4f2b..d65c0cd 100644
--- a/util/ifdtool/ifdtool.h
+++ b/util/ifdtool/ifdtool.h
@@ -35,9 +35,12 @@
CHIPSET_8_SERIES_WELLSBURG,
CHIPSET_9_SERIES_WILDCAT_POINT,
CHIPSET_9_SERIES_WILDCAT_POINT_LP,
- CHIPSET_N_J_SERIES, /* Gemini Lake: N5xxx, J5xxx, N4xxx, J4xxx */
+ CHIPSET_N_J_SERIES_APOLLO_GEMINI_LAKE, /* Apollo Lake, Gemini Lake:
+ * N5xxx, J5xxx, N4xxx, J4xxx */
+ CHIPSET_N_SERIES_JASPER_LAKE, /* Jasper Lake: N6xxx, N51xx, N45xx */
CHIPSET_100_200_SERIES_SUNRISE_POINT, /* 6th-7th gen Core i/o (LP) variants */
- CHIPSET_300_400_SERIES_CANNON_ICE_POINT, /* 8th-10th gen Core i/o (LP) variants */
+ CHIPSET_300_SERIES_CANNON_POINT, /* 8th-9th gen Core i/o (LP) variants */
+ CHIPSET_400_SERIES_ICE_POINT, /* 10th gen Core i/o (LP) variants */
CHIPSET_500_600_SERIES_TIGER_ALDER_POINT, /* 11th-12th gen Core i/o (LP)
* variants onwards */
CHIPSET_C620_SERIES_LEWISBURG,
@@ -54,6 +57,16 @@
PLATFORM_ADL,
};
+/* PSL macros for IFDv2 type platform */
+enum pch_strap_lenth {
+ PSL_APL_GLK = 0x13,
+ PSL_JSL = 0x2a,
+ PSL_CNP = 0x45,
+ PSL_TGP_ADP = 0x46,
+ PSL_ICP = 0x4a,
+ /* Add PSL for newer chipset */
+};
+
#define LAYOUT_LINELEN 80
enum spi_frequency {
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