1 comment:
File src/soc/intel/icelake/graphics.c:
Patch Set #1, Line 48: DDI_A_4_LANES
> Its that simple, I don't think i can able to make you understand that we are trying to get display […]
if soc doesn't have GPU enable then trying to access those registers will cause hang for sure and this function does that specific GT programming in coreboot.
By default coreboot relies on framebuffer which is equivalent to sw rendering mode and till chrome splash screen onwards everything is GPU dependent.
So right now on non-GT parts, we are seeing depthcharge screen using SW rendering but no chrome display.
We are working towards atleast enable chrome OS console mode without using GPU registers
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