Meera Ravindranath uploaded patch set #5 to this change.

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soc/intel/common: Set controller state to active in GSPI init

Set the controller state to D0 during the GSPI sequence,this ensures
the controller is up and active.

BUG=b:135941367
TEST=Verify no timeouts seen during GSPI controller enumeration
     sequence for CML and ICL platforms.

Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I2f95059453ca5565a38650b147590ece4d8bf5ed
---
M src/soc/intel/common/block/gspi/gspi.c
1 file changed, 9 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34449/5

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