Aamir Bohra uploaded patch set #15 to this change.

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mb/google/hatch: Add SoC and EC asl files in DSDT

This implementation adds below code:

1. Add SOC ACPI code in dsdt.asl
   -> platform.asl
   -> globalnvs.asl
   -> cpu.asl
   -> northbridge.asl
   -> southbridge.asl
   -> sleepstate.asl

2. Add chromeos.asl in dsdt.asl

3. Add EC ACPI code in dsdt.asl
   -> superio.asl
   -> ec.asl

4. Remove config for WAK/PTS ACPI method as chromeec
   doesn't implement those.

BUG=b:120914069
TEST=USE="-intel_mrc -bmpblk" emerge-hatch coreboot

Change-Id: Icf1b1d7e34a7e863139c3583903f3b1e2cdc8da6
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/dsdt.asl
M src/mainboard/google/hatch/variants/baseboard/include/baseboard/gpio.h
3 files changed, 39 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/30282/15

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