Jamie Chen has uploaded this change for review.

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soc/intel/cannonlake: Add usb configs for Usb3.1 Gen2 strength

Add usb configs for tuning USB3.1 Gen2 strength.

BUG=b:150515720
BRANCH=none
TEST=build successful in puff

Signed-off-by: Jamie Chen <jamie.chen@intel.com>
Change-Id: Id4860665619095139c329565d433d9eb495cac02
---
M src/soc/intel/cannonlake/fsp_params.c
M src/soc/intel/cannonlake/include/soc/usb.h
2 files changed, 80 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39448/1

diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c
index 80918f1..a6971a1 100644
--- a/src/soc/intel/cannonlake/fsp_params.c
+++ b/src/soc/intel/cannonlake/fsp_params.c
@@ -290,6 +290,36 @@
 			params->Usb3HsioTxDownscaleAmp[i] =
 				config->usb3_ports[i].tx_downscale_amp;
 		}
+#if CONFIG(SOC_INTEL_COMETLAKE)
+		if (config->usb3_ports[i].gen2_tx_rate0_uniq_tran_enable) {
+			params->Usb3HsioTxRate0UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate0UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate0_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate1_uniq_tran_enable) {
+			params->Usb3HsioTxRate1UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate1UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate1_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate2_uniq_tran_enable) {
+			params->Usb3HsioTxRate2UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate2UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate2_uniq_tran;
+		}
+		if (config->usb3_ports[i].gen2_tx_rate3_uniq_tran_enable) {
+			params->Usb3HsioTxRate3UniqTranEnable[i] = 1;
+			params->Usb3HsioTxRate3UniqTran[i] =
+				config->usb3_ports[i].gen2_tx_rate3_uniq_tran;
+		}
+#endif
+		if (config->usb3_ports[i].gen2_rx_tuning_enable) {
+			params->PchUsbHsioRxTuningEnable[i] =
+				config->usb3_ports[i].gen2_rx_tuning_enable;
+			params->PchUsbHsioRxTuningParameters[i] =
+				config->usb3_ports[i].gen2_rx_tuning_params;
+			params->PchUsbHsioFilterSel[i] =
+				config->usb3_ports[i].gen2_rx_filter_sel;
+		}
 	}
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
diff --git a/src/soc/intel/cannonlake/include/soc/usb.h b/src/soc/intel/cannonlake/include/soc/usb.h
index 722a202..e321df5 100644
--- a/src/soc/intel/cannonlake/include/soc/usb.h
+++ b/src/soc/intel/cannonlake/include/soc/usb.h
@@ -133,6 +133,17 @@
 	uint8_t ocpin;
 	uint8_t tx_de_emp;
 	uint8_t tx_downscale_amp;
+	uint8_t gen2_tx_rate0_uniq_tran_enable;
+	uint8_t gen2_tx_rate0_uniq_tran;
+	uint8_t gen2_tx_rate1_uniq_tran_enable;
+	uint8_t gen2_tx_rate1_uniq_tran;
+	uint8_t gen2_tx_rate2_uniq_tran_enable;
+	uint8_t gen2_tx_rate2_uniq_tran;
+	uint8_t gen2_tx_rate3_uniq_tran_enable;
+	uint8_t gen2_tx_rate3_uniq_tran;
+	uint8_t gen2_rx_tuning_enable;
+	uint8_t gen2_rx_tuning_params;
+	uint8_t gen2_rx_filter_sel;
 };
 
 #define USB3_PORT_EMPTY { \
@@ -140,6 +151,17 @@
 	.ocpin            = OC_SKIP, \
 	.tx_de_emp        = 0x00, \
 	.tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 0, \
+	.gen2_tx_rate2_uniq_tran = 0x00, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
+	.gen2_rx_tuning_enable = 0, \
+	.gen2_rx_tuning_params = 0x00, \
+	.gen2_rx_filter_sel = 0x00, \
 }
 
 #define USB3_PORT_DEFAULT(pin) { \
@@ -147,6 +169,34 @@
 	.ocpin            = (pin), \
 	.tx_de_emp        = 0x0, \
 	.tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 0, \
+	.gen2_tx_rate2_uniq_tran = 0x00, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
+	.gen2_rx_tuning_enable = 0, \
+	.gen2_rx_tuning_params = 0x00, \
+	.gen2_rx_filter_sel = 0x00, \
 }
 
+#define USB3_PORT_GEN2_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = 0x0, \
+	.tx_downscale_amp = 0x00, \
+	.gen2_tx_rate0_uniq_tran_enable = 0, \
+	.gen2_tx_rate0_uniq_tran = 0x00, \
+	.gen2_tx_rate1_uniq_tran_enable = 0, \
+	.gen2_tx_rate1_uniq_tran = 0x00, \
+	.gen2_tx_rate2_uniq_tran_enable = 1, \
+	.gen2_tx_rate2_uniq_tran = 0x4C, \
+	.gen2_tx_rate3_uniq_tran_enable = 0, \
+	.gen2_tx_rate3_uniq_tran = 0x00, \
+	.gen2_rx_tuning_enable = 0x0F, \
+	.gen2_rx_tuning_params = 0x15, \
+	.gen2_rx_filter_sel = 0x44, \
+}
 #endif

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