Aaron Durbin (adurbin@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8699
-gerrit
commit 790a42562941ef3dc94621d2f9be600f73c08302 Author: Aaron Durbin adurbin@chromium.org Date: Mon Mar 16 17:30:09 2015 -0500
boostate: use function pointers for scheduling callbacks
Change-Id: I6dc5331c2979d508dde3cd5c3332903d40d8048b Signed-off-by: Aaron Durbin adurbin@chromium.org --- src/arch/arm/ramstage.ld | 1 + src/arch/arm64/ramstage.ld | 2 ++ src/arch/riscv/ramstage.ld | 1 + src/arch/x86/ramstage.ld | 1 + src/cpu/amd/agesa/amd_late_init.c | 1 + src/cpu/amd/pi/amd_late_init.c | 1 + src/drivers/intel/fsp/fsp_util.c | 1 + src/include/bootstate.h | 17 ++++++++++++++++- src/lib/dynamic_cbmem.c | 2 ++ src/lib/hardwaremain.c | 24 +++++++++++++++++------- src/lib/rmodule.ld | 2 ++ src/mainboard/google/rambi/mainboard.c | 1 + src/northbridge/intel/haswell/mrccache.c | 1 + src/northbridge/intel/sandybridge/mrccache.c | 1 + src/soc/intel/baytrail/dptf.c | 1 + src/soc/intel/baytrail/perf_power.c | 1 + src/soc/intel/baytrail/southcluster.c | 1 + src/soc/intel/baytrail/spi.c | 1 + src/soc/intel/broadwell/elog.c | 1 + src/soc/intel/broadwell/finalize.c | 1 + src/soc/intel/broadwell/spi.c | 1 + src/soc/intel/common/mrc_cache.c | 1 + src/southbridge/amd/agesa/hudson/pci.c | 1 + src/southbridge/amd/cimx/sb800/late.c | 1 + src/southbridge/amd/pi/hudson/pci.c | 1 + src/southbridge/intel/common/spi.c | 1 + src/southbridge/intel/lynxpoint/smi.c | 1 + 27 files changed, 61 insertions(+), 8 deletions(-)
diff --git a/src/arch/arm/ramstage.ld b/src/arch/arm/ramstage.ld index 5469509..5e0607d 100644 --- a/src/arch/arm/ramstage.ld +++ b/src/arch/arm/ramstage.ld @@ -64,6 +64,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/arm64/ramstage.ld b/src/arch/arm64/ramstage.ld index de13fcc..784e62d 100644 --- a/src/arch/arm64/ramstage.ld +++ b/src/arch/arm64/ramstage.ld @@ -69,6 +69,8 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; KEEP(*(.bs_init)); + LONG(0); + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/riscv/ramstage.ld b/src/arch/riscv/ramstage.ld index 5d9ba3e..2e97a7e 100644 --- a/src/arch/riscv/ramstage.ld +++ b/src/arch/riscv/ramstage.ld @@ -69,6 +69,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .; *(.rodata) *(.rodata.*) diff --git a/src/arch/x86/ramstage.ld b/src/arch/x86/ramstage.ld index 1c8e8dc..cf60dda 100644 --- a/src/arch/x86/ramstage.ld +++ b/src/arch/x86/ramstage.ld @@ -62,6 +62,7 @@ SECTIONS ecpu_drivers = . ; _bs_init_begin = .; *(.bs_init) + LONG(0); _bs_init_end = .;
*(.rodata) diff --git a/src/cpu/amd/agesa/amd_late_init.c b/src/cpu/amd/agesa/amd_late_init.c index 53c2759..02eb19c 100644 --- a/src/cpu/amd/agesa/amd_late_init.c +++ b/src/cpu/amd/agesa/amd_late_init.c @@ -46,3 +46,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/cpu/amd/pi/amd_late_init.c b/src/cpu/amd/pi/amd_late_init.c index 4b08d1b..d69cb98 100644 --- a/src/cpu/amd/pi/amd_late_init.c +++ b/src/cpu/amd/pi/amd_late_init.c @@ -44,3 +44,4 @@ BOOT_STATE_INIT_ENTRIES(agesa_bscb) = { BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, agesawrapper_post_device, NULL), }; +BOOT_STATE_SCHED_ENTRIES(agesa_bscb); diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index 2a53c25..3c74496 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -322,4 +322,5 @@ BOOT_STATE_INIT_ENTRIES(fsp_hob_find) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, find_fsp_hob_update_mrc, NULL), }; +BOOT_STATE_SCHED_ENTRIES(fsp_hob_find); #endif /* #ifndef __PRE_RAM__ */ diff --git a/src/include/bootstate.h b/src/include/bootstate.h index 202acf7..0738cda 100644 --- a/src/include/bootstate.h +++ b/src/include/bootstate.h @@ -22,6 +22,9 @@ #if !defined(__SMM__) && !defined(__PRE_RAM__)
#include <string.h> +#include <stdlib.h> +#include <stddef.h> +#include <stdint.h>
/* Control debugging of the boot state machine. */ #define BOOT_STATE_DEBUG 0 @@ -157,6 +160,10 @@ int boot_state_sched_on_entry(struct boot_state_callback *bscb, boot_state_t state); int boot_state_sched_on_exit(struct boot_state_callback *bscb, boot_state_t state); +/* Schedule an array of entries of size num. */ +struct boot_state_init_entry; +void boot_state_sched_entries(struct boot_state_init_entry *entries, + size_t num);
/* Block/Unblock the (state, seq) pair from transitioning. Returns 0 on * success < 0 when the phase of the (state,seq) has already ran. */ @@ -181,7 +188,7 @@ struct boot_state_init_entry { #define BOOT_STATE_INIT_ATTR __attribute__ ((used,section (".bs_init")))
#define BOOT_STATE_INIT_ENTRIES(name_) \ - static struct boot_state_init_entry name_[] BOOT_STATE_INIT_ATTR + static struct boot_state_init_entry name_[]
#define BOOT_STATE_INIT_ENTRY(state_, when_, func_, arg_) \ { \ @@ -190,5 +197,13 @@ struct boot_state_init_entry { .bscb = BOOT_STATE_CALLBACK_INIT(func_, arg_), \ }
+#define BOOT_STATE_SCHED_ENTRIES(name_) \ + static void _bscb_sched_ ## name_(void) \ + { \ + boot_state_sched_entries(name_, ARRAY_SIZE(name_)); \ + } \ + static void (*_bscb_sched_ptr_ ## name_)(void) \ + BOOT_STATE_INIT_ATTR = _bscb_sched_ ## name_ + #endif #endif /* BOOTSTATE_H */ diff --git a/src/lib/dynamic_cbmem.c b/src/lib/dynamic_cbmem.c index daa3717..527ce81 100644 --- a/src/lib/dynamic_cbmem.c +++ b/src/lib/dynamic_cbmem.c @@ -456,6 +456,8 @@ BOOT_STATE_INIT_ENTRIES(cbmem_bscb) = { }; #endif
+BOOT_STATE_SCHED_ENTRIES(cbmem_bscb); + void cbmem_add_bootmem(void) { uintptr_t base; diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index 32162eb..96fb64f 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -430,20 +430,30 @@ int boot_state_sched_on_exit(struct boot_state_callback *bscb, return boot_state_sched_callback(state, bscb, BS_ON_EXIT); }
-static void boot_state_schedule_static_entries(void) +void boot_state_sched_entries(struct boot_state_init_entry *entries, size_t num) { - extern struct boot_state_init_entry _bs_init_begin; - extern struct boot_state_init_entry _bs_init_end; - struct boot_state_init_entry *cur; + size_t i;
- cur = &_bs_init_begin; + for (i = 0; i < num; i++) { + struct boot_state_init_entry *cur = &entries[i];
- while (cur != &_bs_init_end) { if (cur->when == BS_ON_ENTRY) boot_state_sched_on_entry(&cur->bscb, cur->state); else boot_state_sched_on_exit(&cur->bscb, cur->state); - cur++; + } +} + +static void boot_state_schedule_static_entries(void) +{ + extern void (*_bs_init_begin[])(void); + void (**f)(void); + + f = &_bs_init_begin[0]; + + while (*f != NULL) { + (*f)(); + f++; } }
diff --git a/src/lib/rmodule.ld b/src/lib/rmodule.ld index f3e7cba..0124c44 100644 --- a/src/lib/rmodule.ld +++ b/src/lib/rmodule.ld @@ -47,6 +47,8 @@ SECTIONS . = ALIGN(8); _bs_init_begin = .; *(.bs_init) + LONG(0); + LONG(0); _bs_init_end = .;
. = ALIGN(8); diff --git a/src/mainboard/google/rambi/mainboard.c b/src/mainboard/google/rambi/mainboard.c index 1290a15..685c92b 100644 --- a/src/mainboard/google/rambi/mainboard.c +++ b/src/mainboard/google/rambi/mainboard.c @@ -185,3 +185,4 @@ static void edp_vdden_cb(void *unused) BOOT_STATE_INIT_ENTRIES(edp_vdden_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, edp_vdden_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(edp_vdden_bscb); diff --git a/src/northbridge/intel/haswell/mrccache.c b/src/northbridge/intel/haswell/mrccache.c index 540bbf6..08d7d89 100644 --- a/src/northbridge/intel/haswell/mrccache.c +++ b/src/northbridge/intel/haswell/mrccache.c @@ -226,6 +226,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif
struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/northbridge/intel/sandybridge/mrccache.c b/src/northbridge/intel/sandybridge/mrccache.c index c84ff82..dd36ad6 100644 --- a/src/northbridge/intel/sandybridge/mrccache.c +++ b/src/northbridge/intel/sandybridge/mrccache.c @@ -227,6 +227,7 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update); #endif
struct mrc_data_container *find_current_mrc_cache(void) diff --git a/src/soc/intel/baytrail/dptf.c b/src/soc/intel/baytrail/dptf.c index 044a807..b05ccbc 100644 --- a/src/soc/intel/baytrail/dptf.c +++ b/src/soc/intel/baytrail/dptf.c @@ -52,3 +52,4 @@ static void dptf_init(void *unused) BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL), }; +BOOT_STATE_SCHED_ENTRIES(dptf_init_bscb); diff --git a/src/soc/intel/baytrail/perf_power.c b/src/soc/intel/baytrail/perf_power.c index 2cde77f..9491617 100644 --- a/src/soc/intel/baytrail/perf_power.c +++ b/src/soc/intel/baytrail/perf_power.c @@ -292,3 +292,4 @@ BOOT_STATE_INIT_ENTRIES(disable_rom_cache_bscb) = { BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, perf_power, NULL), BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, perf_power, NULL), }; +BOOT_STATE_SCHED_ENTRIES(disable_rom_cache_bscb); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index d0569b4..ba61ca4 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -575,3 +575,4 @@ BOOT_STATE_INIT_ENTRIES(finalize_bscb) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, finalize_chipset, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize_bscb); diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index a83fb8e..6861803 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -326,6 +326,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb); #endif
int spi_claim_bus(struct spi_slave *slave) diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index a6a2813..a31a82e 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -136,3 +136,4 @@ static void pch_log_state(void *unused) BOOT_STATE_INIT_ENTRIES(pch_log) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, pch_log_state, NULL) }; +BOOT_STATE_SCHED_ENTRIES(pch_log); diff --git a/src/soc/intel/broadwell/finalize.c b/src/soc/intel/broadwell/finalize.c index 67cba66..24b7d6c 100644 --- a/src/soc/intel/broadwell/finalize.c +++ b/src/soc/intel/broadwell/finalize.c @@ -125,3 +125,4 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, broadwell_finalize, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize); diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 4710271..4636349 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -318,6 +318,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb);
int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index 8f0d18f..99d4a22 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -307,5 +307,6 @@ BOOT_STATE_INIT_ENTRIES(mrc_cache_update) = { BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, update_mrc_cache, NULL), }; +BOOT_STATE_SCHED_ENTRIES(mrc_cache_update);
#endif /* defined(__PRE_RAM__) */ diff --git a/src/southbridge/amd/agesa/hudson/pci.c b/src/southbridge/amd/agesa/hudson/pci.c index 49e2ba6..aa841dd 100644 --- a/src/southbridge/amd/agesa/hudson/pci.c +++ b/src/southbridge/amd/agesa/hudson/pci.c @@ -49,6 +49,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update);
static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/amd/cimx/sb800/late.c b/src/southbridge/amd/cimx/sb800/late.c index 2125027..dfcf167 100644 --- a/src/southbridge/amd/cimx/sb800/late.c +++ b/src/southbridge/amd/cimx/sb800/late.c @@ -330,6 +330,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update);
/** * @brief SB Cimx entry point sbBeforePciInit wrapper diff --git a/src/southbridge/amd/pi/hudson/pci.c b/src/southbridge/amd/pi/hudson/pci.c index e8836e4..3188155 100644 --- a/src/southbridge/amd/pi/hudson/pci.c +++ b/src/southbridge/amd/pi/hudson/pci.c @@ -52,6 +52,7 @@ BOOT_STATE_INIT_ENTRIES(pci_irq_update) = { BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL), }; +BOOT_STATE_SCHED_ENTRIES(pci_irq_update);
static struct pci_operations lops_pci = { .set_subsystem = 0, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index d6ab01a..1a75241 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -368,6 +368,7 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRIES(spi_init_bscb) = { BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL), }; +BOOT_STATE_SCHED_ENTRIES(spi_init_bscb);
int spi_claim_bus(struct spi_slave *slave) { diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 94abf5f..7424cb3 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -139,5 +139,6 @@ BOOT_STATE_INIT_ENTRIES(finalize) = { BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL), }; +BOOT_STATE_SCHED_ENTRIES(finalize);
#endif