Subrata Banik has uploaded this change for review.
soc/intel/cmn/graphics: Use GSM size for calculating GTT offset
This patch overrides the assumption being made by the GFX PEIM blob
between version 1029 and 103x to fix some issue where GTT offset
has calculated based on the eDP panel resoultion rather relying on
the GSM memory limit.
Now this is causing major blocker for CrOS as GFX PEIM latest version
is no more working with existing OS (causing reboot or blank display).
To fix this issue, coreboot tries to perform an override to restore
PANEL_SURF register to the original value which has calculated based
on GSM size.
BUG=b:314887266
TEST=Able to boot to OS where display is functional with latest FSP
(w/ GFX PEIM 1035).
Change-Id: Ied5af0faad73d0c88cab70dee6fe731f1a14653b
Signed-off-by: Subrata Banik <subratabanik@google.com>
---
M src/soc/intel/common/block/graphics/graphics.c
1 file changed, 20 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/80405/1
diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c
index ef4b269..acf5dc5 100644
--- a/src/soc/intel/common/block/graphics/graphics.c
+++ b/src/soc/intel/common/block/graphics/graphics.c
@@ -3,6 +3,7 @@
#include <acpi/acpi.h>
#include <assert.h>
#include <bootmode.h>
+#include <commonlib/helpers.h>
#include <console/console.h>
#include <device/mmio.h>
#include <device/pci.h>
@@ -12,6 +13,7 @@
#include <drivers/intel/gma/opregion.h>
#include <intelblocks/cfg.h>
#include <intelblocks/graphics.h>
+#include <intelblocks/systemagent.h>
#include <fsp/graphics.h>
#include <soc/pci_devs.h>
#include <types.h>
@@ -33,6 +35,9 @@
#define GFX_MBUS_HASHING_MODE BIT(30)
#define GFX_MBUS_JOIN_PIPE_SEL (BIT(28) | BIT(27) | BIT(26))
+#define GFX_PLANE_SURF 0x7019C
+#define GFX_PLANE_SEL(x, y) (GFX_PLANE_SURF + (y << 12) + ((x - 1) << 8))
+
/* SoC Overrides */
__weak void graphics_soc_panel_init(struct device *dev)
{
@@ -280,21 +285,36 @@
}
}
+static uint32_t get_gtt_offset(void)
+{
+ const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
+ if (!dev)
+ return 0;
+
+ return (((uintptr_t)4 * GiB) - sa_get_dsm_size(dev));
+}
+
static void graphics_join_mbus(void)
{
enum display_type type = get_external_display_status();
+ uint32_t gtt_offset = get_gtt_offset();
uint32_t hashing_mode = 0; /* 2x2 */
if (type == INTERNAL_DISPLAY_ONLY) {
hashing_mode = GFX_MBUS_HASHING_MODE; /* 1x4 */
/* Only eDP pipes is joining the MBUS */
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
+ graphics_gtt_write(GFX_PLANE_SEL(1, PIPE_A), gtt_offset);
} else if (type == DUAL_DISPLAY) {
/* All pipes are joining the MBUS */
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_A), PIPE_A, GFX_MBUS_JOIN | hashing_mode);
+ graphics_gtt_write(GFX_PLANE_SEL(1, PIPE_A), gtt_offset);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_B), PIPE_B, GFX_MBUS_JOIN | hashing_mode);
+ graphics_gtt_write(GFX_PLANE_SEL(1, PIPE_B), gtt_offset);
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_C), PIPE_C, GFX_MBUS_JOIN | hashing_mode);
+ graphics_gtt_write(GFX_PLANE_SEL(1, PIPE_C), gtt_offset);
#if CONFIG(INTEL_GMA_VERSION_2)
graphics_gtt_rmw(GFX_MBUS_SEL(PIPE_D), PIPE_D, GFX_MBUS_JOIN | hashing_mode);
+ graphics_gtt_write(GFX_PLANE_SEL(1, PIPE_D), gtt_offset);
#endif
} else {
/* No pipe joins the MBUS */
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