Attention is currently required from: Subrata Banik, Tarun Tuli.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/76203?usp=email )
Change subject: soc/intel: Drop the suffixes from ADL and RPL CPUID macros ......................................................................
soc/intel: Drop the suffixes from ADL and RPL CPUID macros
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID.
Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com --- M src/include/cpu/intel/cpu_ids.h M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/common/block/cpu/mp_init.c 3 files changed, 22 insertions(+), 22 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/76203/1
diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 4501c1a..1fa6780 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -58,11 +58,11 @@ #define CPUID_SAPPHIRERAPIDS_SP_Ex 0x806f8 #define CPUID_ELKHARTLAKE_A0 0x90660 #define CPUID_ELKHARTLAKE_B0 0x90661 -#define CPUID_ALDERLAKE_S_A0 0x90670 -#define CPUID_ALDERLAKE_S_B0 0x90671 -#define CPUID_ALDERLAKE_S_C0 0x90672 -#define CPUID_ALDERLAKE_S_G0 0x90674 -#define CPUID_ALDERLAKE_S_H0 0x90675 +#define CPUID_ALDERLAKE_A0 0x90670 +#define CPUID_ALDERLAKE_B0 0x90671 +#define CPUID_ALDERLAKE_C0 0x90672 +#define CPUID_ALDERLAKE_G0 0x90674 +#define CPUID_ALDERLAKE_H0 0x90675 #define CPUID_ALDERLAKE_J0 0x906a0 #define CPUID_ALDERLAKE_Q0 0x906a1 #define CPUID_ALDERLAKE_K0 0x906a2 @@ -73,11 +73,11 @@ #define CPUID_METEORLAKE_A0_2 0xa06a1 #define CPUID_METEORLAKE_B0 0xa06a2 #define CPUID_METEORLAKE_C0 0xa06a4 -#define CPUID_RAPTORLAKE_S_A0 0xb0670 -#define CPUID_RAPTORLAKE_S_B0 0xb0671 -#define CPUID_RAPTORLAKE_S_C0_1 0xb0672 -#define CPUID_RAPTORLAKE_S_C0_2 0xb0675 -#define CPUID_RAPTORLAKE_P_J0 0xb06a2 -#define CPUID_RAPTORLAKE_P_Q0 0xb06a3 +#define CPUID_RAPTORLAKE_A0 0xb0670 +#define CPUID_RAPTORLAKE_B0 0xb0671 +#define CPUID_RAPTORLAKE_C0_1 0xb0672 +#define CPUID_RAPTORLAKE_C0_2 0xb0675 +#define CPUID_RAPTORLAKE_J0 0xb06a2 +#define CPUID_RAPTORLAKE_Q0 0xb06a3
#endif /* CPU_INTEL_CPU_IDS_H */ diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index f118a89..2942547 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -34,10 +34,10 @@ { CPUID_ALDERLAKE_S_C0, "Alderlake-S C0 Platform" }, { CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" }, { CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" }, - { CPUID_RAPTORLAKE_S_A0, "Raptorlake-S A0 Platform" }, - { CPUID_RAPTORLAKE_S_B0, "Raptorlake-S B0 Platform" }, - { CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" }, - { CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" }, + { CPUID_RAPTORLAKE_A0, "Raptorlake-S A0 Platform" }, + { CPUID_RAPTORLAKE_B0, "Raptorlake-S B0 Platform" }, + { CPUID_RAPTORLAKE_J0, "Raptorlake-P J0 Platform" }, + { CPUID_RAPTORLAKE_Q0, "Raptorlake-P Q0 Platform" }, };
static struct { diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index 8f3ffc2..918795a 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -74,19 +74,19 @@ { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ELKHARTLAKE_B0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_JASPERLAKE_A0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_ALDERLAKE_S_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_ALDERLAKE_A0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_J0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_K0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_L0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0, CPUID_EXACT_MATCH_MASK }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_A0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_B0, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_C0_1, CPUID_EXACT_MATCH_MASK }, - { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_C0_2, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_J0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_Q0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_A0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_B0, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_C0_1, CPUID_EXACT_MATCH_MASK }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_C0_2, CPUID_EXACT_MATCH_MASK }, CPU_TABLE_END };