Subrata Banik has uploaded this change for review.

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soc/intel/icelake: Make use of common thermal code for ICL

This patch ports CB:34522 and CB:33147 changes from CNL to ICL.

TEST=Build and boot dragonegg

Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
M src/soc/intel/icelake/Kconfig
M src/soc/intel/icelake/finalize.c
3 files changed, 14 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/34649/1
diff --git a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
index b3b93f5..f49e1c9 100644
--- a/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/dragonegg/variants/baseboard/devicetree.cb
@@ -148,6 +148,7 @@
#| | required to set up a BAR |
#| | for TPM communication |
#| | before memory is up |
+ #| pch_thermal_trip | PCH Trip Temperature |
#+-------------------+---------------------------+

register "common_soc_config" = "{
@@ -165,6 +166,7 @@
.sda_hold = 36,
}
},
+ .pch_thermal_trip = "77",
}"

# GPIO PM programming
@@ -181,7 +183,7 @@
device pci 00.0 on end # Host Bridge
device pci 02.0 on end # Integrated Graphics Device
device pci 04.0 off end # SA Thermal device
- device pci 12.0 off end # Thermal Subsystem
+ device pci 12.0 on end # Thermal Subsystem
device pci 12.5 off end # UFS SCS
device pci 12.6 off end # GSPI #2
device pci 14.0 on
diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig
index 99000bb..3ad50cf 100644
--- a/src/soc/intel/icelake/Kconfig
+++ b/src/soc/intel/icelake/Kconfig
@@ -51,6 +51,7 @@
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SMM
select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP
+ select SOC_INTEL_COMMON_BLOCK_THERMAL
select SOC_INTEL_COMMON_PCH_BASE
select SOC_INTEL_COMMON_RESET
select SSE2
diff --git a/src/soc/intel/icelake/finalize.c b/src/soc/intel/icelake/finalize.c
index c969f3b..086787d 100644
--- a/src/soc/intel/icelake/finalize.c
+++ b/src/soc/intel/icelake/finalize.c
@@ -23,6 +23,7 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/tco.h>
+#include <intelblocks/thermal.h>
#include <reg_script.h>
#include <spi-generic.h>
#include <soc/p2sb.h>
@@ -63,6 +64,15 @@
tco_lockdown();

/*
+ * Set low maximum temp threshold value used for dynamic thermal sensor
+ * shutdown consideration.
+ *
+ * If Dynamic Thermal Shutdown is enabled then PMC logic shuts down the
+ * thermal sensor when CPU is in a C-state and DTS Temp <= LTT.
+ */
+ pch_thermal_configuration();
+
+ /*
* Disable ACPI PM timer based on dt policy
*
* Disabling ACPI PM timer is necessary for XTAL OSC shutdown.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85
Gerrit-Change-Number: 34649
Gerrit-PatchSet: 1
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-MessageType: newchange