Patch set 3:Code-Review +2
1 comment:
File src/mainboard/purism/librem_cnl/romstage.c:
Patch Set #2, Line 104: cannonlake_memcfg_init(mem_cfg, &memcfg);
the SPD addressing is different when using coreboot to read the SPD via smbus vs FSP, so that alone […]
It would need to be thought. Anyway, no reason to block this change.
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