Tim Wawrzynczak submitted this change.

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Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Angel Pons: Looks good to me, approved
Documentation: Add section about 'hidden' devices to 4.13 release notes

CB:41384 (SHA dbcf7b16219df0c04401b8fcd6a780174a7df305) added some new
functionality to devicetree files ("hidden PCI devices"). It's a decent
enough semantic change that it should be added to the release notes for
the 4.13 release.

Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
M Documentation/releases/coreboot-4.13-relnotes.md
1 file changed, 15 insertions(+), 0 deletions(-)

diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md
index 94e93bb..1d8839f 100644
--- a/Documentation/releases/coreboot-4.13-relnotes.md
+++ b/Documentation/releases/coreboot-4.13-relnotes.md
@@ -13,4 +13,19 @@
Significant changes
-------------------

+### Hidden PCI devices
+
+This new functionality takes advantage of the existing 'hidden' keyword in the
+devicetree. Since no existing boards were using the keyword, its usage was
+repurposed to make dealing with some unique PCI devices easier. The particular
+case here is Intel's PMC (Power Management Controller). During the FSP-S run,
+the PMC device is made hidden, meaning that its config space looks as if there
+is no device there (Vendor ID reads as 0xFFFF_FFFF). However, the device does
+have fixed resources, both MMIO and I/O. These were previously recorded in
+different places (MMIO was typically an SA fixed resource, and I/O was treated
+as an LPC resource). With this change, when a device in the tree is marked as
+'hidden', it is not probed (`pci_probe_dev()`) but rather assumed to exist so
+that its resources can be placed in a more natural location. This also adds the
+ability for the device to participate in SSDT generation.
+
### Add significant changes here

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I52969f63dbc492afd32279176cbcfc2b76d7ac33
Gerrit-Change-Number: 41563
Gerrit-PatchSet: 4
Gerrit-Owner: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Aaron Durbin <adurbin@chromium.org>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Duncan Laurie <dlaurie@chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: merged