Felix Held has uploaded this change for review.
x4x/raminit_ddr23: use MCHBAR AND/OR/AND_OR macros [1/2]
When using reproducible builds and coreboot crossgcc 6.3.0, the checksum of the
resulting binary doesn't change with applying this commit.
Change-Id: I057abe314622e92000c7e4ff2faa4595edb5244b
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
---
M src/northbridge/intel/x4x/raminit_ddr23.c
1 file changed, 224 insertions(+), 222 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/27717/1
diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c
index 6cc5e32..71130e0 100644
--- a/src/northbridge/intel/x4x/raminit_ddr23.c
+++ b/src/northbridge/intel/x4x/raminit_ddr23.c
@@ -53,7 +53,7 @@
{
u8 i, j;
u32 reg32;
- MCHBAR16(0xc1c) = MCHBAR16(0xc1c) | (1 << 15);
+ MCHBAR16_OR(0xc1c, (1 << 15));
static const u32 clkxtab[6][3][13] = {
/* MEMCLK 400 N/A */
@@ -125,7 +125,7 @@
}
MCHBAR32(0xc50) = reg32;
MCHBAR32(0xc54) = clkxtab[i][j][2];
- MCHBAR8(0xc08) = MCHBAR8(0xc08) | (1 << 7);
+ MCHBAR8_OR(0xc08, (1 << 7));
MCHBAR32(0x6d8) = clkxtab[i][j][3];
MCHBAR32(0x6e0) = clkxtab[i][j][3];
MCHBAR32(0x6dc) = clkxtab[i][j][4];
@@ -143,29 +143,29 @@
static void setioclk_dram(struct sysinfo *s)
{
MCHBAR32(0x1bc) = 0x08060402;
- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x200;
- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x100;
- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) | 0x20;
- MCHBAR16(0x1c0) = MCHBAR16(0x1c0) & ~1;
+ MCHBAR16_OR(0x1c0, 0x200);
+ MCHBAR16_OR(0x1c0, 0x100);
+ MCHBAR16_OR(0x1c0, 0x20);
+ MCHBAR16_AND(0x1c0, ~1);
switch (s->selected_timings.mem_clk) {
default:
case MEM_CLOCK_800MHz:
case MEM_CLOCK_1066MHz:
- MCHBAR8(0x5d9) = (MCHBAR8(0x5d9) & ~0x2) | 0x2;
- MCHBAR8(0x9d9) = (MCHBAR8(0x9d9) & ~0x2) | 0x2;
- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xc0;
- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xe0;
- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0xa0;
+ MCHBAR8_AND_OR(0x5d9, ~0x2, 0x2);
+ MCHBAR8_AND_OR(0x9d9, ~0x2, 0x2);
+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xc0);
+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xe0);
+ MCHBAR8_AND_OR(0x189, ~0xf0, 0xa0);
break;
case MEM_CLOCK_667MHz:
case MEM_CLOCK_1333MHz:
- MCHBAR8(0x5d9) = MCHBAR8(0x5d9) & ~0x2;
- MCHBAR8(0x9d9) = MCHBAR8(0x9d9) & ~0x2;
- MCHBAR8(0x189) = (MCHBAR8(0x189) & ~0xf0) | 0x40;
+ MCHBAR8_AND(0x5d9, ~0x2);
+ MCHBAR8_AND(0x9d9, ~0x2);
+ MCHBAR8_AND_OR(0x189, ~0xf0, 0x40);
break;
}
- MCHBAR32(0x594) = MCHBAR32(0x594) | (1 << 31);
- MCHBAR32(0x994) = MCHBAR32(0x994) | (1 << 31);
+ MCHBAR32_OR(0x594, 1 << 31);
+ MCHBAR32_OR(0x994, 1 << 31);
}
static void launch_dram(struct sysinfo *s)
@@ -253,14 +253,14 @@
MCHBAR32(0x400*i + 0x220) = launch1;
MCHBAR32(0x400*i + 0x224) = launch2;
MCHBAR32(0x400*i + 0x21c) = 0;
- MCHBAR32(0x400*i + 0x248) = MCHBAR32(0x400*i + 0x248) | (1 << 23);
+ MCHBAR32_OR(0x400*i + 0x248, 1 << 23);
}
- MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0x58000000) | 0x48000000;
- MCHBAR32(0x2c0) = MCHBAR32(0x2c0) | 0x1e0;
- MCHBAR32(0x2c4) = (MCHBAR32(0x2c4) & ~0xf) | 0xc;
+ MCHBAR32_AND_OR(0x2c0, ~0x58000000, 0x48000000);
+ MCHBAR32_OR(0x2c0, 0x1e0);
+ MCHBAR32_AND_OR(0x2c4, ~0xf, 0xc);
if (s->spd_type == DDR3)
- MCHBAR32(0x2c4) = MCHBAR32(0x2c4) | 0x100;
+ MCHBAR32_OR(0x2c4, 0x100);
}
static void clkset0(u8 ch, const struct dll_setting *setting)
@@ -541,10 +541,10 @@
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
- MCHBAR8(0x400*i + 0x26f) = MCHBAR8(0x400*i + 0x26f) | 0x3;
- MCHBAR8(0x400*i + 0x228) = (MCHBAR8(0x400*i + 0x228) & ~0x7) | 0x2;
- MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf0)
- | (0 << 4); /* tWL - x ?? */
+ MCHBAR8_OR(0x400*i + 0x26f, 0x3);
+ MCHBAR8_AND_OR(0x400*i + 0x228, ~0x7, 0x2);
+ /* tWL - x ?? */
+ MCHBAR8_AND_OR(0x400*i + 0x240, ~0xf0, 0 << 4);
MCHBAR8(0x400*i + 0x240) = (MCHBAR8(0x400*i + 0x240) & ~0xf) |
adjusted_cas;
MCHBAR16(0x400*i + 0x265) = (MCHBAR16(0x400*i + 0x265) & ~0x3f00) |
@@ -628,13 +628,13 @@
}
reg16 |= flag1 << 8;
reg16 |= flag2 << 9;
- MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x1ff) | reg16;
+ MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x1ff, reg16);
MCHBAR16(0x400*i + 0x25e) = 0x15a5;
- MCHBAR32(0x400*i + 0x265) = MCHBAR32(0x400*i + 0x265) & ~0x1f;
- MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0x000fffff) |
- (0x3f << 14) | lut1[s->selected_timings.mem_clk];
- MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) | 1;
- MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3;
+ MCHBAR32_AND(0x400*i + 0x265, ~0x1f);
+ MCHBAR32_AND_OR(0x400*i + 0x269, ~0x000fffff,
+ (0x3f << 14) | lut1[s->selected_timings.mem_clk]);
+ MCHBAR8_OR(0x400*i + 0x274, 1);
+ MCHBAR8_AND(0x400*i + 0x24c, ~0x3);
reg16 = 0;
if (s->spd_type == DDR2) {
@@ -666,36 +666,36 @@
reg16 &= 0x7;
reg16 += twl + 9;
reg16 <<= 10;
- MCHBAR16(0x400*i + 0x24d) = (MCHBAR16(0x400*i + 0x24d) & ~0x7c00) | reg16;
- MCHBAR8(0x400*i + 0x267) = (MCHBAR8(0x400*i + 0x267) & ~0x3f) | 0x13;
- MCHBAR8(0x400*i + 0x268) = (MCHBAR8(0x400*i + 0x268) & ~0xff) | 0x4a;
+ MCHBAR16_AND_OR(0x400*i + 0x24d, ~0x7c00, reg16);
+ MCHBAR8_AND_OR(0x400*i + 0x267, ~0x3f, 0x13);
+ MCHBAR8_AND_OR(0x400*i + 0x268, ~0xff, 0x4a);
reg16 = (MCHBAR16(0x400*i + 0x269) & 0xc000) >> 2;
reg16 += 2 << 12;
reg16 |= (0x15 << 6) | 0x1f;
- MCHBAR16(0x400*i + 0x26d) = (MCHBAR16(0x400*i + 0x26d) & ~0x7fff) | reg16;
+ MCHBAR16_AND_OR(0x400*i + 0x26d, ~0x7fff, reg16);
reg32 = (1 << 25) | (6 << 27);
- MCHBAR32(0x400*i + 0x269) = (MCHBAR32(0x400*i + 0x269) & ~0xfa300000) | reg32;
- MCHBAR8(0x400*i + 0x271) = MCHBAR8(0x400*i + 0x271) & ~0x80;
- MCHBAR8(0x400*i + 0x274) = MCHBAR8(0x400*i + 0x274) & ~0x6;
+ MCHBAR32_AND_OR(0x400*i + 0x269, ~0xfa300000, reg32);
+ MCHBAR8_AND(0x400*i + 0x271, ~0x80);
+ MCHBAR8_AND(0x400*i + 0x274, ~0x6);
} // END EACH POPULATED CHANNEL
reg16 = 0x1f << 5;
reg16 |= 0xe << 10;
- MCHBAR16(0x125) = (MCHBAR16(0x125) & ~0x3fe0) | reg16;
- MCHBAR16(0x127) = (MCHBAR16(0x127) & ~0x7ff) | 0x540;
- MCHBAR8(0x129) = MCHBAR8(0x129) | 0x1f;
- MCHBAR8(0x12c) = MCHBAR8(0x12c) | 0xa0;
- MCHBAR32(0x241) = (MCHBAR32(0x241) & ~0x1ffff) | 0x11;
- MCHBAR32(0x641) = (MCHBAR32(0x641) & ~0x1ffff) | 0x11;
- MCHBAR8(0x246) = MCHBAR8(0x246) & ~0x10;
- MCHBAR8(0x646) = MCHBAR8(0x646) & ~0x10;
+ MCHBAR16_AND_OR(0x125, ~0x3fe0, reg16);
+ MCHBAR16_AND_OR(0x127, ~0x7ff, 0x540);
+ MCHBAR8_OR(0x129, 0x1f);
+ MCHBAR8_OR(0x12c, 0xa0);
+ MCHBAR32_AND_OR(0x241, ~0x1ffff, 0x11);
+ MCHBAR32_AND_OR(0x641, ~0x1ffff, 0x11);
+ MCHBAR8_AND(0x246, ~0x10);
+ MCHBAR8_AND(0x646, ~0x10);
MCHBAR32(0x120) = (2 << 29) | (1 << 28) | (1 << 23) | 0xd7f5f;
reg8 = (u8)((MCHBAR32(0x252) & 0x1e000) >> 13);
- MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf0) | (reg8 << 4);
+ MCHBAR8_AND_OR(0x12d, ~0xf0, reg8 << 4);
reg8 = (u8)((MCHBAR32(0x258) & 0x1e0000) >> 17);
- MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8;
+ MCHBAR8_AND_OR(0x12d, ~0xf, reg8);
MCHBAR8(0x12f) = 0x4c;
reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9);
if (s->spd_type == DDR3) {
@@ -706,8 +706,8 @@
reg16 &= 0x1ff;
reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9);
}
- MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32;
- MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2;
+ MCHBAR32_AND_OR(0x6c0, ~0xffffff00, reg32);
+ MCHBAR8_AND_OR(0x6c4, ~0x7, 0x2);
}
static void program_dll(struct sysinfo *s)
@@ -719,11 +719,11 @@
const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04,
0x08, 0x10 };
- MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04;
- MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8;
- MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f;
- MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x8020) | 0x100;
- MCHBAR8(0x194) = (MCHBAR8(0x194) & ~0x77) | 0x33;
+ MCHBAR16_AND_OR(0x180, ~0x7e06, 0xc04);
+ MCHBAR16_AND_OR(0x182, ~0x3ff, 0xc8);
+ MCHBAR16_AND_OR(0x18a, ~0x1f1f, 0x0f0f);
+ MCHBAR16_AND_OR(0x1b4, ~0x8020, 0x100);
+ MCHBAR8_AND_OR(0x194, ~0x77, 0x33);
switch (s->selected_timings.mem_clk) {
default:
case MEM_CLOCK_667MHz:
@@ -737,41 +737,41 @@
reg16 = (0x7 << 9) | 0x7;
break;
}
- MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16;
- MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010;
+ MCHBAR16_AND_OR(0x19c, ~0x1e0f, reg16);
+ MCHBAR16_AND_OR(0x19c, ~0x2030, 0x2010);
udelay(1);
- MCHBAR16(0x198) = MCHBAR16(0x198) & ~0x100;
+ MCHBAR16_AND(0x198, ~0x100);
- MCHBAR16(0x1c8) = (MCHBAR16(0x1c8) & ~0x1f) | 0xd;
+ MCHBAR16_AND_OR(0x1c8, ~0x1f, 0xd);
udelay(1);
- MCHBAR8(0x190) = MCHBAR8(0x190) & ~1;
+ MCHBAR8_AND(0x190, ~1);
udelay(1); // 533ns
- MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x11554000;
+ MCHBAR32_AND(0x198, ~0x11554000);
udelay(1);
- MCHBAR32(0x198) = MCHBAR32(0x198) & ~0x1455;
+ MCHBAR32_AND(0x198, ~0x1455);
udelay(1);
- MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x1c;
- MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x1c;
+ MCHBAR8_AND(0x583, ~0x1c);
+ MCHBAR8_AND(0x983, ~0x1c);
udelay(1); // 533ns
- MCHBAR8(0x583) = MCHBAR8(0x583) & ~0x3;
- MCHBAR8(0x983) = MCHBAR8(0x983) & ~0x3;
+ MCHBAR8_AND(0x583, ~0x3);
+ MCHBAR8_AND(0x983, ~0x3);
udelay(1); // 533ns
// ME related
- MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff)
- | (s->spd_type == DDR2 ? 0x551803 : 0x555801);
+ MCHBAR32_AND_OR(0x1a0, ~0x7ffffff,
+ s->spd_type == DDR2 ? 0x551803 : 0x555801);
- MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800;
+ MCHBAR16_AND(0x1b4, ~0x800);
if (s->spd_type == DDR2) {
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0;
+ MCHBAR8_OR(0x1a8, 0xf0);
} else { /* DDR3 */
reg8 = 0x9; /* 0x9 << 4 ?? */
if (s->dimms[0].ranks == 2)
reg8 &= ~0x80;
if (s->dimms[3].ranks == 2)
reg8 &= ~0x10;
- MCHBAR8(0x1a8) = (MCHBAR8(0x1a8) & ~0xf0) | reg8;
+ MCHBAR8_AND_OR(0x1a8, ~0xf0, reg8);
}
FOR_EACH_CHANNEL(i) {
@@ -787,8 +787,8 @@
reg32 |= 0x111 << r;
}
- MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32;
- MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1;
+ MCHBAR32_AND_OR(0x400*i + 0x59c, ~0xfff, reg32);
+ MCHBAR8_AND(0x400*i + 0x594, ~1);
if (s->spd_type == DDR2) {
if (!CHANNEL_IS_POPULATED(s->dimms, i)) {
@@ -813,8 +813,8 @@
} else {
die("Unhandled case\n");
}
- MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0)
- & ~0x3f000000) | ((u32)(reg8 << 24));
+ MCHBAR32_AND_OR(0x400*i + 0x5a0, ~0x3f000000,
+ (u32)(reg8 << 24));
} else { /* DDR3 */
FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) {
@@ -828,25 +828,25 @@
} // END EACH CHANNEL
if (s->spd_type == DDR2) {
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1;
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
+ MCHBAR8_OR(0x1a8, 1);
+ MCHBAR8_AND(0x1a8, ~0x4);
} else { /* DDR3 */
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~1;
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;
+ MCHBAR8_AND(0x1a8, ~1);
+ MCHBAR8_OR(0x1a8, 0x4);
}
// Update DLL timing
- MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80;
- MCHBAR8(0x1a4) = MCHBAR8(0x1a4) | 0x40;
- MCHBAR16(0x5f0) = (MCHBAR16(0x5f0) & ~0x400) | 0x400;
+ MCHBAR8_AND(0x1a4, ~0x80);
+ MCHBAR8_OR(0x1a4, 0x40);
+ MCHBAR16_AND_OR(0x5f0, ~0x400, 0x400);
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
- MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc;
- MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc;
- MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0)
- | (s->spd_type == DDR2 ? 0x70 : 0x60);
- MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff)
- | (s->spd_type == DDR2 ? 0x5555 : 0xa955);
+ MCHBAR16_AND_OR(0x400*i + 0x5f0, ~0x3fc, 0x3fc);
+ MCHBAR32_AND(0x400*i + 0x5fc, ~0xcccccccc);
+ MCHBAR8_AND_OR(0x400*i + 0x5d9, ~0xf0,
+ s->spd_type == DDR2 ? 0x70 : 0x60);
+ MCHBAR16_AND_OR(0x400*i + 0x590, ~0xffff,
+ s->spd_type == DDR2 ? 0x5555 : 0xa955);
}
FOR_EACH_POPULATED_CHANNEL(s->dimms, i) {
@@ -881,12 +881,12 @@
}
// XXX if not async mode
- MCHBAR16(0x180) = MCHBAR16(0x180) & ~0x8200;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4;
+ MCHBAR16_AND(0x180, ~0x8200);
+ MCHBAR8_OR(0x180, 0x4);
j = 0;
for (i = 0; i < 16; i++) {
- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
+ MCHBAR8_OR(0x180, 0x10);
while (MCHBAR8(0x180) & 0x10)
;
if (MCHBAR32(0x184) == 0xffffffff) {
@@ -906,8 +906,8 @@
j = 0;
i++;
for (; i < 16; i++) {
- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x4;
+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
+ MCHBAR8_OR(0x180, 0x4);
while (MCHBAR8(0x180) & 0x10)
;
if (MCHBAR32(0x184) == 0) {
@@ -916,8 +916,8 @@
}
}
for (; i < 16; i++) {
- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
+ MCHBAR8_OR(0x180, 0x10);
while (MCHBAR8(0x180) & 0x10)
;
if (MCHBAR32(0x184) == 0xffffffff) {
@@ -929,8 +929,8 @@
}
}
if (j < 2) {
- MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
+ MCHBAR8_AND(0x1c8, ~0x1f);
+ MCHBAR8_OR(0x180, 0x10);
while (MCHBAR8(0x180) & 0x10)
;
j = 2;
@@ -938,7 +938,7 @@
}
if (j < 2) {
- MCHBAR8(0x1c8) = MCHBAR8(0x1c8) & ~0x1f;
+ MCHBAR8_AND(0x1c8, ~0x1f);
async = 1;
}
@@ -968,7 +968,7 @@
if (async != 1)
reg8 = MCHBAR8(0x188) & 0x1e;
- MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80;
+ MCHBAR8_AND(0x180, ~0x80);
if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz)
|| (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz
@@ -978,8 +978,8 @@
i = (i + 10) % 14;
else /* DDR3 */
i = (i + 3) % 12;
- MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i;
- MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10;
+ MCHBAR8_AND_OR(0x1c8, ~0x1f, i);
+ MCHBAR8_OR(0x180, 0x10);
while (MCHBAR8(0x180) & 0x10)
;
}
@@ -993,7 +993,7 @@
MCHBAR8(0x188) = reg8;
if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz)
- MCHBAR8(0x18c) = MCHBAR8(0x18c) | 1;
+ MCHBAR8_OR(0x18c, 1);
}
static void select_default_dq_dqs_settings(struct sysinfo *s)
@@ -1145,8 +1145,8 @@
MCHBAR32(0x400*i + addr[j]) =
(MCHBAR32(0x400*i + addr[j]) & ~0xff000)
| 0xaa000;
- MCHBAR16(0x400*i + 0x320) = (MCHBAR16(0x400*i + 0x320)
- & ~0xffff) | 0x6666;
+ MCHBAR16_AND_OR(0x400*i + 0x320, ~0xffff,
+ 0x6666);
for (k = 0; k < 8; k++) {
MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2)) =
(MCHBAR32(0x400*i + addr[j] + 0xe + (k << 2))
@@ -1196,23 +1196,23 @@
MCHBAR8(0x400*i + addr[j]) = (MCHBAR8(0x400*i + addr[j]) & ~1) | bit[j];
}
reg8 = (s->spd_type == DDR2) ? 0x12 : 0x36;
- MCHBAR8(0x400*i + 0x45a) = (MCHBAR8(0x400*i + 0x45a) & ~0x3f) | reg8;
- MCHBAR8(0x400*i + 0x45e) = (MCHBAR8(0x400*i + 0x45e) & ~0x3f) | reg8;
- MCHBAR8(0x400*i + 0x462) = (MCHBAR8(0x400*i + 0x462) & ~0x3f) | reg8;
- MCHBAR8(0x400*i + 0x466) = (MCHBAR8(0x400*i + 0x466) & ~0x3f) | reg8;
+ MCHBAR8_AND_OR(0x400*i + 0x45a, ~0x3f, reg8);
+ MCHBAR8_AND_OR(0x400*i + 0x45e, ~0x3f, reg8);
+ MCHBAR8_AND_OR(0x400*i + 0x462, ~0x3f, reg8);
+ MCHBAR8_AND_OR(0x400*i + 0x466, ~0x3f, reg8);
} // END EACH POPULATED CHANNEL
- MCHBAR32(0x134) = (MCHBAR32(0x134) & ~0x63c00) | 0x63c00;
- MCHBAR16(0x174) = (MCHBAR16(0x174) & ~0x63ff) | 0x63ff;
+ MCHBAR32_AND_OR(0x134, ~0x63c00, 0x63c00);
+ MCHBAR16_AND_OR(0x174, ~0x63ff, 0x63ff);
MCHBAR16(0x178) = 0x0135;
- MCHBAR32(0x130) = (MCHBAR32(0x130) & ~0x7bdffe0) | 0x7a9ffa0;
+ MCHBAR32_AND_OR(0x130, ~0x7bdffe0, 0x7a9ffa0);
if (!CHANNEL_IS_POPULATED(s->dimms, 0))
- MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 27);
+ MCHBAR32_AND(0x130, ~(1 << 27));
if (!CHANNEL_IS_POPULATED(s->dimms, 1))
- MCHBAR32(0x130) = MCHBAR32(0x130) & ~(1 << 28);
+ MCHBAR32_AND(0x130, ~(1 << 28));
- MCHBAR8(0x130) = MCHBAR8(0x130) | 1;
+ MCHBAR8_OR(0x130, 1);
}
static void program_odt(struct sysinfo *s)
@@ -1306,8 +1306,8 @@
* by the SPD.
*/
/* Set rank 0-3 populated */
- MCHBAR32(C0CKECTRL) = (MCHBAR32(C0CKECTRL) & ~1) | 0xf00000;
- MCHBAR32(C1CKECTRL) = (MCHBAR32(C1CKECTRL) & ~1) | 0xf00000;
+ MCHBAR32_AND_OR(C0CKECTRL, ~1, 0xf00000);
+ MCHBAR32_AND_OR(C1CKECTRL, ~1, 0xf00000);
/* Set size of each rank to 128M */
MCHBAR16(C0DRA01) = 0x0101;
MCHBAR16(C0DRA23) = 0x0101;
@@ -1323,7 +1323,7 @@
/* In stacked mode the last present rank on ch1 needs to have its
size doubled in c1drbx */
MCHBAR16(C1DRB3) = 0x0010;
- MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;
+ MCHBAR8_OR(0x111, STACKED_MEM);
MCHBAR32(0x104) = 0;
MCHBAR16(0x102) = 0x400;
MCHBAR8(0x110) = (2 << 5) | (3 << 3);
@@ -1371,8 +1371,8 @@
data8 = (u8)mirror_shift_bit(data8, 4);
}
- MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | data8;
- MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | data8;
+ MCHBAR8_AND_OR(0x271, ~0x3e, data8);
+ MCHBAR8_AND_OR(0x671, ~0x3e, data8);
data32 = val;
if (s->spd_type == DDR3 && (r & 1)
&& s->dimms[ch * 2 + (r >> 1)].mirrored) {
@@ -1384,8 +1384,8 @@
rubbish = read32((void *)((data32 | addr)));
udelay(10);
- MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD;
- MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD;
+ MCHBAR8_AND_OR(0x271, ~0x3e, NORMALOP_CMD);
+ MCHBAR8_AND_OR(0x671, ~0x3e, NORMALOP_CMD);
}
static void jedec_ddr2(struct sysinfo *s)
@@ -1611,23 +1611,22 @@
MCHBAR32(0x208) = c0dra;
MCHBAR32(0x608) = c1dra;
- MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0);
- MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0);
+ MCHBAR8_AND_OR(0x262, ~0xf0, (rankpop0 << 4) & 0xf0);
+ MCHBAR8_AND_OR(0x662, ~0xf0, (rankpop1 << 4) & 0xf0);
if (s->spd_type == DDR3) {
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
/* ZQCAL enable */
- MCHBAR32(0x269 + 0x400 * ch) =
- MCHBAR32(0x269 + 0x400 * ch) | (1 << 26);
+ MCHBAR32_OR(0x269 + 0x400 * ch, 1 << 26);
}
}
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) ||
ONLY_DIMMB_IS_POPULATED(s->dimms, 0))
- MCHBAR8(0x260) = MCHBAR8(0x260) | 1;
+ MCHBAR8_OR(0x260, 1);
if (ONLY_DIMMA_IS_POPULATED(s->dimms, 1) ||
ONLY_DIMMB_IS_POPULATED(s->dimms, 1))
- MCHBAR8(0x660) = MCHBAR8(0x660) | 1;
+ MCHBAR8_OR(0x660, 1);
// DRB
lastrank_ch1 = 0;
@@ -1671,10 +1670,10 @@
size_me = ME_UMA_SIZEMB;
if (s->stacked_mode) {
- MCHBAR8(0x111) = MCHBAR8(0x111) | STACKED_MEM;
+ MCHBAR8_OR(0x111, STACKED_MEM);
} else {
- MCHBAR8(0x111) = MCHBAR8(0x111) & ~STACKED_MEM;
- MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4);
+ MCHBAR8_AND(0x111, ~STACKED_MEM);
+ MCHBAR8_OR(0x111, 1 << 4);
}
if (s->stacked_mode) {
@@ -1690,7 +1689,7 @@
/* Set ME UMA size in MiB */
MCHBAR16(0x100) = size_me;
/* Set ME UMA Present bit */
- MCHBAR32(0x111) = MCHBAR32(0x111) | 1;
+ MCHBAR32_OR(0x111, 1);
}
dual_channel_size = MIN(size_ch0 - size_me, size_ch1) * 2;
}
@@ -1822,21 +1821,21 @@
MCHBAR32(0xfbc) = 0xf;
MCHBAR32(0xfc4) = 0xfe22244;
MCHBAR8(0x12f) = 0x5c;
- MCHBAR8(0xfb0) = (MCHBAR8(0xfb0) & ~1) | 1;
+ MCHBAR8_OR(0xfb0, 1);
if (s->selected_timings.mem_clk <= MEM_CLOCK_800MHz)
- MCHBAR8(0x12f) = MCHBAR8(0x12f) | 0x2;
+ MCHBAR8_OR(0x12f, 0x2);
else
- MCHBAR8(0x12f) = MCHBAR8(0x12f) & ~0x2;
- MCHBAR8(0x6c0) = (MCHBAR8(0x6c0) & ~0xf0) | 0xa0;
+ MCHBAR8_AND(0x12f, ~0x2);
+ MCHBAR8_AND_OR(0x6c0, ~0xf0, 0xa0);
MCHBAR32(0xfa8) = 0x30d400;
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;
+ MCHBAR8_OR(0x400*ch + 0x26c, 1);
MCHBAR32(0x400*ch + 0x278) = 0x88141881;
MCHBAR16(0x400*ch + 0x27c) = 0x0041;
MCHBAR8(0x400*ch + 0x292) = 0xf2;
- MCHBAR16(0x400*ch + 0x272) = MCHBAR16(0x400*ch + 0x272) | 0x100;
- MCHBAR8(0x400*ch + 0x243) = (MCHBAR8(0x400*ch + 0x243) & ~0x2) | 1;
+ MCHBAR16_OR(0x400*ch + 0x272, 0x100);
+ MCHBAR8_AND_OR(0x400*ch + 0x243, ~0x2, 1);
MCHBAR32(0x400*ch + 0x288) = 0x8040200;
MCHBAR32(0x400*ch + 0x28c) = 0xff402010;
MCHBAR32(0x400*ch + 0x290) = 0x4f2091c;
@@ -1855,7 +1854,7 @@
} else if (s->selected_timings.fsb_clk == FSB_CLOCK_1066MHz) {
reg32 &= ~0x10000;
}
- MCHBAR32(0xfa4) = (MCHBAR32(0xfa4) & ~0x219100c3) | reg32;
+ MCHBAR32_AND_OR(0xfa4, ~0x219100c3, reg32);
reg32 = 0x44a00;
switch (s->selected_timings.fsb_clk) {
case FSB_CLOCK_1333MHz:
@@ -1881,7 +1880,7 @@
reg32 = 0x8f038000;
if (s->selected_timings.fsb_clk == FSB_CLOCK_1333MHz)
reg32 &= ~0x4000000;
- MCHBAR32(0x40) = (MCHBAR32(0x40) & ~0x8f038000) | reg32;
+ MCHBAR32_AND_OR(0x40, ~0x8f038000, reg32);
reg32 = 0x00013001;
if (s->selected_timings.fsb_clk < FSB_CLOCK_1333MHz)
reg32 |= 0x20000;
@@ -1954,47 +1953,50 @@
MCHBAR32(0x14) = 0x0010691f;
MCHBAR32(0x18) = 0xdf6437f7;
MCHBAR32(0x1c) = 0x0;
- MCHBAR32(0x24) = (MCHBAR32(0x24) & ~0xe0000000) | 0x60000000;
- MCHBAR32(0x44) = (MCHBAR32(0x44) & ~0x1fef0000) | 0x6b0000;
+ MCHBAR32_AND_OR(0x24, ~0xe0000000, 0x60000000);
+ MCHBAR32_AND_OR(0x44, ~0x1fef0000, 0x6b0000);
MCHBAR16(0x115) = (u16) reg1;
- MCHBAR32(0x117) = (MCHBAR32(0x117) & ~0xffffff) | reg2;
+ MCHBAR32_AND_OR(0x117, ~0xffffff, reg2);
MCHBAR8(0x124) = 0x7;
- MCHBAR16(0x12a) = (MCHBAR16(0x12a) & 0) | 0x80;
- MCHBAR8(0x12c) = (MCHBAR8(0x12c) & 0) | 0xa0;
- MCHBAR16(0x174) = MCHBAR16(0x174) & ~(1 << 15);
- MCHBAR16(0x188) = (MCHBAR16(0x188) & ~0x1f00) | 0x1f00;
- MCHBAR8(0x18c) = MCHBAR8(0x18c) & ~0x8;
- MCHBAR8(0x192) = (MCHBAR8(0x192) & ~1) | 1;
- MCHBAR8(0x193) = (MCHBAR8(0x193) & ~0xf) | 0xf;
- MCHBAR16(0x1b4) = (MCHBAR16(0x1b4) & ~0x480) | 0x80;
- MCHBAR16(0x210) = (MCHBAR16(0x210) & ~0x1fff) | 0x3f; // | clockgatingiii
- MCHBAR32(0x6d1) = (MCHBAR32(0x6d1) & ~0xff03ff) | 0x100 | clkgate;
- MCHBAR8(0x212) = (MCHBAR8(0x212) & ~0x7f) | 0x7f;
- MCHBAR32(0x2c0) = (MCHBAR32(0x2c0) & ~0xffff0) | 0xcc5f0;
- MCHBAR8(0x2c4) = (MCHBAR8(0x2c4) & ~0x70) | 0x70;
- MCHBAR32(0x2d1) = (MCHBAR32(0x2d1) & ~0xffffff) | 0xff2831; // | clockgatingi
+ // not sure if dummy reads are needed
+ MCHBAR16_AND_OR(0x12a, 0, 0x80);
+ MCHBAR8_AND_OR(0x12c, 0, 0xa0);
+ MCHBAR16_AND(0x174, ~(1 << 15));
+ MCHBAR16_AND_OR(0x188, ~0x1f00, 0x1f00);
+ MCHBAR8_AND(0x18c, ~0x8);
+ MCHBAR8_OR(0x192, 1);
+ MCHBAR8_OR(0x193, 0xf);
+ MCHBAR16_AND_OR(0x1b4, ~0x480, 0x80);
+ MCHBAR16_AND_OR(0x210, ~0x1fff, 0x3f); // | clockgatingiii
+ // non-aligned access: possible bug?
+ MCHBAR32_AND_OR(0x6d1, ~0xff03ff, 0x100 | clkgate);
+ MCHBAR8_AND_OR(0x212, ~0x7f, 0x7f);
+ MCHBAR32_AND_OR(0x2c0, ~0xffff0, 0xcc5f0);
+ MCHBAR8_AND_OR(0x2c4, ~0x70, 0x70);
+ // non-aligned access: possible bug?
+ MCHBAR32_AND_OR(0x2d1, ~0xffffff, 0xff2831); // | clockgatingi
MCHBAR32(0x2d4) = 0x40453600;
MCHBAR32(0x300) = 0xc0b0a08;
MCHBAR32(0x304) = 0x6040201;
- MCHBAR32(0x30c) = (MCHBAR32(0x30c) & ~0x43c0f) | 0x41405;
+ MCHBAR32_AND_OR(0x30c, ~0x43c0f, 0x41405);
MCHBAR16(0x610) = reg3;
MCHBAR16(0x612) = reg4;
- MCHBAR32(0x62c) = (MCHBAR32(0x62c) & ~0xc000000) | 0x4000000;
+ MCHBAR32_AND_OR(0x62c, ~0xc000000, 0x4000000);
MCHBAR32(0xae4) = 0;
- MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0xf0000) | 0x10000;
+ MCHBAR32_AND_OR(0xc00, ~0xf0000, 0x10000);
MCHBAR32(0xf00) = 0x393a3b3c;
MCHBAR32(0xf04) = 0x3d3e3f40;
MCHBAR32(0xf08) = 0x393a3b3c;
MCHBAR32(0xf0c) = 0x3d3e3f40;
- MCHBAR32(0xf18) = MCHBAR32(0xf18) & ~0xfff00001;
+ MCHBAR32_AND(0xf18, ~0xfff00001);
MCHBAR32(0xf48) = 0xfff0ffe0;
MCHBAR32(0xf4c) = 0xffc0ff00;
MCHBAR32(0xf50) = 0xfc00f000;
MCHBAR32(0xf54) = 0xc0008000;
- MCHBAR32(0xf6c) = (MCHBAR32(0xf6c) & ~0xffff0000) | 0xffff0000;
- MCHBAR32(0xfac) = MCHBAR32(0xfac) & ~0x80000000;
- MCHBAR32(0xfb8) = MCHBAR32(0xfb8) & ~0xff000000;
- MCHBAR32(0xfbc) = (MCHBAR32(0xfbc) & ~0x7f800) | 0xf000;
+ MCHBAR32_AND_OR(0xf6c, ~0xffff0000, 0xffff0000);
+ MCHBAR32_AND(0xfac, ~0x80000000);
+ MCHBAR32_AND(0xfb8, ~0xff000000);
+ MCHBAR32_AND_OR(0xfbc, ~0x7f800, 0xf000);
MCHBAR32(0x1104) = 0x3003232;
MCHBAR32(0x1108) = 0x74;
if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz)
@@ -2010,31 +2012,31 @@
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
MCHBAR8(0x400*ch + 0x239) = twl + 15;
MCHBAR16(0x400*ch + 0x23c) = x23c;
- MCHBAR32(0x400*ch + 0x248) = (MCHBAR32(0x400*ch + 0x248) & ~0x706033) | 0x406033;
- MCHBAR32(0x400*ch + 0x260) = (MCHBAR32(0x400*ch + 0x260) & ~(1 << 16)) | (1 << 16);
+ MCHBAR32_AND_OR(0x400*ch + 0x248, ~0x706033, 0x406033);
+ MCHBAR32_AND_OR(0x400*ch + 0x260, ~(1 << 16), 1 << 16);
MCHBAR8(0x400*ch + 0x264) = x264;
- MCHBAR8(0x400*ch + 0x592) = (MCHBAR8(0x400*ch + 0x592) & ~0x3f) | (0x3c & x592);
- MCHBAR8(0x400*ch + 0x593) = (MCHBAR8(0x400*ch + 0x593) & ~0x1f) | 0x1e;
+ MCHBAR8_AND_OR(0x400*ch + 0x592, ~0x3f, 0x3c & x592);
+ MCHBAR8_AND_OR(0x400*ch + 0x593, ~0x1f, 0x1e);
}
for (lane = 0; lane < 8; lane++)
- MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3);
+ MCHBAR8_AND(0x561 + (lane << 2), ~(1 << 3));
}
static void software_ddr3_reset(struct sysinfo *s)
{
printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n");
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x02;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02;
- MCHBAR8(0x5da) = (MCHBAR8(0x5da) & ~0x03) | 1;
+ MCHBAR8_OR(0x1a8, 0x02);
+ MCHBAR8_AND(0x5da, ~0x80);
+ MCHBAR8_AND(0x1a8, ~0x02);
+ MCHBAR8_AND_OR(0x5da, ~0x03, 1);
udelay(200);
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;
+ MCHBAR8_AND(0x1a8, ~0x02);
+ MCHBAR8_OR(0x5da, 0x80);
+ MCHBAR8_AND(0x5da, ~0x80);
udelay(500);
- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x03;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x03;
+ MCHBAR8_OR(0x5da, 0x03);
+ MCHBAR8_AND(0x5da, ~0x03);
/* After write leveling the dram needs to be reset and reinitialised */
jedec_ddr3(s);
}
@@ -2051,17 +2053,17 @@
| PMSTS_BOTH_SELFREFRESH;
// Clear host clk gate reg
- MCHBAR32(0x1c) = MCHBAR32(0x1c) | 0xffffffff;
+ MCHBAR32_OR(0x1c, 0xffffffff);
// Select type
if (s->spd_type == DDR2)
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4;
+ MCHBAR8_AND(0x1a8, ~0x4);
else
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4;
+ MCHBAR8_OR(0x1a8, 0x4);
// Set freq
- MCHBAR32(0xc00) = (MCHBAR32(0xc00) & ~0x70) |
- (s->selected_timings.mem_clk << 4) | (1 << 10);
+ MCHBAR32_AND_OR(0xc00, ~0x70,
+ (s->selected_timings.mem_clk << 4) | (1 << 10));
// Overwrite freq if chipset rejects it
s->selected_timings.mem_clk = (MCHBAR8(0xc00) & 0x70) >> 4;
@@ -2104,7 +2106,7 @@
// RCOMP update
if (s->boot_path != BOOT_PATH_WARM_RESET) {
- while ((MCHBAR8(0x130) & 1) != 0)
+ while (MCHBAR8(0x130) & 1)
;
printk(BIOS_DEBUG, "Done RCOMP update\n");
}
@@ -2113,36 +2115,36 @@
// IOBUFACT
if (CHANNEL_IS_POPULATED(s->dimms, 0)) {
- MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f;
- MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 0x7;
+ MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
+ MCHBAR8_OR(0x5d8, 0x7);
}
if (CHANNEL_IS_POPULATED(s->dimms, 1)) {
if (pci_read_config8(PCI_DEV(0, 0, 0), 0x8) < 2) {
- MCHBAR8(0x5dd) = (MCHBAR8(0x5dd) & ~0x3f) | 0x3f;
- MCHBAR8(0x5d8) = MCHBAR8(0x5d8) | 1;
+ MCHBAR8_AND_OR(0x5dd, ~0x3f, 0x3f);
+ MCHBAR8_OR(0x5d8, 1);
}
- MCHBAR8(0x9dd) = (MCHBAR8(0x9dd) & ~0x3f) | 0x3f;
- MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7;
+ MCHBAR8_OR(0x9dd, 0x3f);
+ MCHBAR8_OR(0x9d8, 0x7);
}
/* DDR3 reset */
if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) {
printk(BIOS_DEBUG, "DDR3 Reset.\n");
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80;
+ MCHBAR8_AND(0x1a8, ~0x2);
+ MCHBAR8_OR(0x5da, 0x80);
udelay(500);
- MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2;
- MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80;
+ MCHBAR8_AND(0x1a8, ~0x2);
+ MCHBAR8_AND(0x5da, ~0x80);
udelay(500);
}
// Pre jedec
- MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2;
+ MCHBAR8_OR(0x40, 0x2);
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR32(0x400*ch + 0x260) = MCHBAR32(0x400*ch + 0x260) | (1 << 27);
+ MCHBAR32_OR(0x400*ch + 0x260, 1 << 27);
}
- MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf000) | 0xf000;
- MCHBAR16(0x212) = (MCHBAR16(0x212) & ~0xf00) | 0xf00;
+ MCHBAR16_OR(0x212, 0xf000);
+ MCHBAR16_OR(0x212, 0xf00);
printk(BIOS_DEBUG, "Done pre-jedec\n");
// JEDEC reset
@@ -2163,7 +2165,7 @@
}
// After JEDEC reset
- MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2;
+ MCHBAR8_AND(0x40, ~0x2);
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
reg32 = (2 << 18);
reg32 |= post_jedec_tab[s->selected_timings.fsb_clk]
@@ -2180,23 +2182,23 @@
[s->selected_timings.mem_clk - MEM_CLOCK_667MHz][1]
<< 8;
}
- MCHBAR32(0x400*ch + 0x274) = (MCHBAR32(0x400*ch + 0x274) & ~0xfff00) | reg32;
- MCHBAR8(0x400*ch + 0x274) = MCHBAR8(0x400*ch + 0x274) & ~0x80;
- MCHBAR8(0x400*ch + 0x26c) = MCHBAR8(0x400*ch + 0x26c) | 1;
+ MCHBAR32_AND_OR(0x400*ch + 0x274, ~0xfff00, reg32);
+ MCHBAR8_AND(0x400*ch + 0x274, ~0x80);
+ MCHBAR8_OR(0x400*ch + 0x26c, 1);
MCHBAR32(0x400*ch + 0x278) = 0x88141881;
MCHBAR16(0x400*ch + 0x27c) = 0x41;
MCHBAR8(0x400*ch + 0x292) = 0xf2;
- MCHBAR8(0x400*ch + 0x271) = (MCHBAR8(0x400*ch + 0x271) & ~0xe) | 0xe;
+ MCHBAR8_OR(0x400*ch + 0x271, 0xe);
}
- MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x8;
- MCHBAR8(0x2c3) = MCHBAR8(0x2c3) | 0x40;
- MCHBAR8(0x2c4) = MCHBAR8(0x2c4) | 0x4;
+ MCHBAR8_OR(0x2c4, 0x8);
+ MCHBAR8_OR(0x2c3, 0x40);
+ MCHBAR8_OR(0x2c4, 0x4);
printk(BIOS_DEBUG, "Done post-jedec\n");
// Set DDR init complete
FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) {
- MCHBAR32(0x400*ch + 0x268) = (MCHBAR32(0x400*ch + 0x268) & ~0xc0000000) | 0xc0000000;
+ MCHBAR32_OR(0x400*ch + 0x268, 0xc0000000);
}
// Receive enable
@@ -2205,14 +2207,14 @@
// Finish rcven
FOR_EACH_CHANNEL(ch) {
- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) & ~0xe;
- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x2;
- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x4;
- MCHBAR8(0x400*ch + 0x5d8) = MCHBAR8(0x400*ch + 0x5d8) | 0x8;
+ MCHBAR8_AND(0x400*ch + 0x5d8, ~0xe);
+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x2);
+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x4);
+ MCHBAR8_OR(0x400*ch + 0x5d8, 0x8);
}
- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;
- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) & ~0x80;
- MCHBAR8(0x5dc) = MCHBAR8(0x5dc) | 0x80;
+ MCHBAR8_OR(0x5dc, 0x80);
+ MCHBAR8_AND(0x5dc, ~0x80);
+ MCHBAR8_OR(0x5dc, 0x80);
// Dummy writes / reads
if (s->boot_path == BOOT_PATH_NORMAL) {
@@ -2260,9 +2262,9 @@
printk(BIOS_DEBUG, "Done enhanced mode\n");
// Periodic RCOMP
- MCHBAR16(0x160) = (MCHBAR16(0x160) & ~0xfff) | 0x999;
- MCHBAR16(0x1b4) = MCHBAR16(0x1b4) | 0x3000;
- MCHBAR8(0x130) = MCHBAR8(0x130) | 0x82;
+ MCHBAR16_AND_OR(0x160, ~0xfff, 0x999);
+ MCHBAR16_OR(0x1b4, 0x3000);
+ MCHBAR8_OR(0x130, 0x82);
printk(BIOS_DEBUG, "Done PRCOMP\n");
// Power settings
@@ -2277,11 +2279,11 @@
if (ME_UMA_SIZEMB != 0) {
if (RANK_IS_POPULATED(s->dimms, 0, 0)
|| RANK_IS_POPULATED(s->dimms, 1, 0))
- MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 0);
+ MCHBAR8_OR(0xa2f, 1 << 0);
if (RANK_IS_POPULATED(s->dimms, 0, 1)
|| RANK_IS_POPULATED(s->dimms, 1, 1))
- MCHBAR8(0xa2f) = MCHBAR8(0xa2f) | (1 << 1);
- MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26);
+ MCHBAR8_OR(0xa2f, 1 << 1);
+ MCHBAR32_OR(0xa30, 1 << 26);
}
printk(BIOS_DEBUG, "Done raminit\n");
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