Patch Set 34:

Patch Set 27:

Patch Set 27:

Patch Set 27:

Problem here is can't identify which CPU PCIE is used if just check 06.0.. Still need a flag for CPU port?

	# Enable CPU PCIE RP 1 using PEG CLK 0
	register "cpu_pcie_rp[CPU_RP(1)]" = "{
		.flags = PCIE_RP_CLK_REQ_UNUSED,
		.clk_src  = 0,
        }"
	# Enable PCU PCIE PEG Slot 1 and 2
	register "cpu_pcie_rp[CPU_RP(2)]" = "{
		.flags = PCIE_RP_CLK_REQ_UNUSED,
		.clk_src  = 3,
        }"
	register "cpu_pcie_rp[CPU_RP(3)]" = "{
		.flags = PCIE_RP_CLK_REQ_UNUSED,
		.clk_src  = 4,
        }"

in the EDS, I see:
"The ADL-P processor PCI Express* has two interfaces:
• One 8-lane (x8) port supporting PCIE to gen 5.0 or below.
• Two 4-lane (x4) port supporting PCIE gen 4.0 or below"

and I read the rest to say that:
00:01.0 (pcie5) has 1 x8 port (pcie5 or lower)
00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower)
00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)

also for the PCIE5 port:
"Support is also provided for narrow width and use devices with lower number of lanes (that is, usage on x4 configuration), however further bifurcation is not supported"

and for the PCIE4 ports only support 1x4 and 1x4 reversed, so no way to get bifurcation to support x8 on those ports I think.

@Tim, could you point out to me where has this information?
@Furquan, from the information provided by Tim, we may need check 01.0 06.0 06.2 for CPU_RP 1/2/3. If so, it will skip 6.1 may need to change in the cpu_rp check..

@Meera and Subrata, could you help confirm this? But I didn't see adlrvp turn on 00:01.0 and 00:06.2.
> 00:01.0 (pcie5) has 1 x8 port (pcie5 or lower)
> 00:06.0 (pci4_0) has 1 x4 port (pcie4 or lower)
> 00:06.2 (pci4_1) has 1 x4 port (pcie4 or lower)

sure it's in the processor EDS vol. 1, chapter 7 about PCIe

Oh, yes... I just read the GPE parts but miss the before.. Looks like your are correct but different series of CPU have different ports. And we don't know the reversal mapping if control by ME or FSP?

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