Elyes HAOUAS has uploaded this change for review.
src: Move IA32_MISC_ENABLE to x86/msr.h
Change-Id: I5d39a1834610ef054c14ce1a7637f44e715d0654
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/cpu/intel/fsp_model_206ax/model_206ax.h
M src/cpu/intel/fsp_model_406dx/model_406dx.h
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/model_1067x/model_1067x_init.c
M src/cpu/intel/model_106cx/model_106cx_init.c
M src/cpu/intel/model_2065x/model_2065x.h
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/model_6ex/model_6ex_init.c
M src/cpu/intel/model_6fx/model_6fx_init.c
M src/cpu/intel/speedstep/speedstep.c
M src/cpu/intel/turbo/turbo.c
M src/cpu/via/nano/nano_init.c
M src/include/cpu/intel/speedstep.h
M src/include/cpu/intel/turbo.h
M src/include/cpu/x86/msr.h
M src/northbridge/intel/nehalem/early_init.c
M src/soc/intel/apollolake/cpu.c
M src/soc/intel/baytrail/include/soc/msr.h
M src/soc/intel/baytrail/tsc_freq.c
M src/soc/intel/braswell/include/soc/msr.h
M src/soc/intel/braswell/tsc_freq.c
M src/soc/intel/broadwell/include/soc/msr.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/denverton_ns/cpu.c
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/fsp_baytrail/include/soc/msr.h
M src/soc/intel/fsp_baytrail/tsc_freq.c
27 files changed, 36 insertions(+), 51 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/28855/1
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index 29a868d..eb4d6a9 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -25,7 +25,6 @@
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index 169744a..194fc12 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -26,7 +26,6 @@
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 7533a6b..b4e8c88 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -40,7 +40,6 @@
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c
index 0d9169b..ce5dac4 100644
--- a/src/cpu/intel/model_1067x/model_1067x_init.c
+++ b/src/cpu/intel/model_1067x/model_1067x_init.c
@@ -190,7 +190,7 @@
const u32 sub_cstates = cpuid_edx(5);
- msr = rdmsr(IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 3); /* TM1 enable */
if (tm2)
msr.lo |= (1 << 13); /* TM2 enable */
@@ -220,11 +220,11 @@
if (rdmsr(MSR_FSB_CLOCK_VCC).hi & (1 << (63 - 32)))
msr.hi &= ~(1 << (38 - 32));
- wrmsr(IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
if (eist) {
msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
- wrmsr(IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
}
}
diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c
index dd7bbc8..6bf21fd 100644
--- a/src/cpu/intel/model_106cx/model_106cx_init.c
+++ b/src/cpu/intel/model_106cx/model_106cx_init.c
@@ -56,7 +56,6 @@
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
-#define IA32_MISC_ENABLE 0x1a0
static void configure_misc(void)
{
msr_t msr;
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index de1282b..445d313 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -25,7 +25,6 @@
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_FERR_CAPABILITY 0x1f1
#define FERR_ENABLE (1 << 0)
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 4a40ac3..cbfa6ae 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -25,7 +25,6 @@
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
#define IA32_PLATFORM_DCA_CAP 0x1f8
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_TEMPERATURE_TARGET 0x1a2
#define IA32_ENERGY_PERFORMANCE_BIAS 0x1b0
#define ENERGY_POLICY_PERFORMANCE 0
diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c
index 96830c4..8d68b9e 100644
--- a/src/cpu/intel/model_6ex/model_6ex_init.c
+++ b/src/cpu/intel/model_6ex/model_6ex_init.c
@@ -58,7 +58,6 @@
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
-#define IA32_MISC_ENABLE 0x1a0
static void configure_misc(void)
{
msr_t msr;
diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c
index a1433f6..9dd1223 100644
--- a/src/cpu/intel/model_6fx/model_6fx_init.c
+++ b/src/cpu/intel/model_6fx/model_6fx_init.c
@@ -59,7 +59,6 @@
wrmsr(MSR_PMG_IO_CAPTURE_ADDR, msr);
}
-#define IA32_MISC_ENABLE 0x1a0
#define IA32_PECI_CTL 0x5a0
static void configure_misc(void)
diff --git a/src/cpu/intel/speedstep/speedstep.c b/src/cpu/intel/speedstep/speedstep.c
index 441f2a3..43d5b5a 100644
--- a/src/cpu/intel/speedstep/speedstep.c
+++ b/src/cpu/intel/speedstep/speedstep.c
@@ -72,7 +72,7 @@
msr = rdmsr(MSR_FSB_CLOCK_VCC);
if ((msr.hi & (1 << (63 - 32))) &&
/* supported and */
- !(rdmsr(IA32_MISC_ENABLES).hi & (1 << (38 - 32)))) {
+ !(rdmsr(IA32_MISC_ENABLE).hi & (1 << (38 - 32)))) {
/* not disabled */
params->turbo = SPEEDSTEP_STATE_FROM_MSR(msr.hi, state_mask);
params->turbo.is_turbo = 1;
diff --git a/src/cpu/intel/turbo/turbo.c b/src/cpu/intel/turbo/turbo.c
index 5583c46..c31f4c0 100644
--- a/src/cpu/intel/turbo/turbo.c
+++ b/src/cpu/intel/turbo/turbo.c
@@ -68,7 +68,7 @@
cpuid_regs = cpuid(CPUID_LEAF_PM);
turbo_cap = !!(cpuid_regs.eax & PM_CAP_TURBO_MODE);
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
turbo_en = !(msr.hi & H_MISC_DISABLE_TURBO);
if (!turbo_cap && turbo_en) {
@@ -97,9 +97,9 @@
/* Only possible if turbo is available but hidden */
if (get_turbo_state() == TURBO_DISABLED) {
/* Clear Turbo Disable bit in Misc Enables */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.hi &= ~H_MISC_DISABLE_TURBO;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Update cached turbo state */
set_global_turbo_state(TURBO_ENABLED);
@@ -115,9 +115,9 @@
msr_t msr;
/* Set Turbo Disable bit in Misc Enables */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.hi |= H_MISC_DISABLE_TURBO;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Update cached turbo state */
set_global_turbo_state(TURBO_UNAVAILABLE);
diff --git a/src/cpu/via/nano/nano_init.c b/src/cpu/via/nano/nano_init.c
index c8b054c..985a3c7 100644
--- a/src/cpu/via/nano/nano_init.c
+++ b/src/cpu/via/nano/nano_init.c
@@ -28,7 +28,6 @@
#define MODEL_NANO_3000_B0 0x8
#define MODEL_NANO_3000_B2 0xa
-#define MSR_IA32_MISC_ENABLE 0x000001a0
#define NANO_MYSTERIOUS_MSR 0x120e
static void nano_finish_fid_vid_transition(void)
@@ -94,9 +93,9 @@
{
msr_t msr;
/* Enable Powersaver */
- msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
- wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Enable 6 bit or 7-bit VRM support
* This MSR is not documented by VIA docs, other than setting these
@@ -114,24 +113,24 @@
nano_set_max_fid_vid();
/* Enable TM3 */
- msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 3) | (1 << 13) );
- wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
u8 stepping = ( cpuid_eax(0x1) ) &0xf;
if (stepping >= MODEL_NANO_3000_B0) {
/* Hello Nano 3000. The Terminator needs a CPU upgrade */
/* Enable C1e, C2e, C3e, and C4e states */
- msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= ( (1 << 25) | (1 << 26) | (1 << 31)); /* C1e, C2e, C3e */
msr.hi |= (1 << 0); /* C4e */
- wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
}
/* Lock on Powersaver */
- msr = rdmsr(MSR_IA32_MISC_ENABLE);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 20);
- wrmsr(MSR_IA32_MISC_ENABLE, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
}
static void nano_init(struct device *dev)
diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h
index d8b73f2..2413b44 100644
--- a/src/include/cpu/intel/speedstep.h
+++ b/src/include/cpu/intel/speedstep.h
@@ -36,7 +36,7 @@
/* Speedstep related MSRs */
#define MSR_THERM2_CTL 0x19D
-#define IA32_MISC_ENABLES 0x1A0
+#define IA32_MISC_ENABLE 0x1A0
#define MSR_EBC_FREQUENCY_ID 0x2c
#define MSR_FSB_FREQ 0xcd
#define MSR_FSB_CLOCK_VCC 0xce
diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h
index 58f4831..0880ebb 100644
--- a/src/include/cpu/intel/turbo.h
+++ b/src/include/cpu/intel/turbo.h
@@ -20,7 +20,6 @@
#define CPUID_LEAF_PM 6
#define PM_CAP_TURBO_MODE (1 << 1)
-#define MSR_IA32_MISC_ENABLES 0x1a0
/* Disable the Monitor Mwait FSM feature */
#define MONITOR_MWAIT_DIS_MASK 0x40000
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index b37eb83..02c698d 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -25,6 +25,9 @@
#define IA32_PERF_STATUS 0x198
#define IA32_PERF_CTL 0x199
#define IA32_THERM_INTERRUPT 0x19b
+#define IA32_MISC_ENABLE 0x1a0
+/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
+#define BURST_MODE_DISABLE (1 << 6)
#define MSR_IA32_PAT 0x277
#define IA32_BIOS_UPDT_TRIG 0x79
#define IA32_BIOS_SIGN_ID 0x8b
diff --git a/src/northbridge/intel/nehalem/early_init.c b/src/northbridge/intel/nehalem/early_init.c
index 0a9b408..1ebb2a5 100644
--- a/src/northbridge/intel/nehalem/early_init.c
+++ b/src/northbridge/intel/nehalem/early_init.c
@@ -110,11 +110,11 @@
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
- m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m = rdmsr(IA32_MISC_ENABLE);
m.hi &= ~0x00000040;
m.lo |= 0x10000;
- wrmsr(MSR_IA32_MISC_ENABLES, m);
+ wrmsr(IA32_MISC_ENABLE, m);
}
m = rdmsr(MSR_FSB_CLOCK_VCC);
@@ -124,9 +124,9 @@
m.lo = (m.lo & ~0xff) | reg8;
wrmsr(IA32_PERF_CTL, m);
- m = rdmsr(MSR_IA32_MISC_ENABLES);
+ m = rdmsr(IA32_MISC_ENABLE);
m.lo |= 0x10000;
- wrmsr(MSR_IA32_MISC_ENABLES, m);
+ wrmsr(IA32_MISC_ENABLE, m);
}
void nehalem_early_initialization(int chipset_type)
diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c
index caa3bbf..928679f 100644
--- a/src/soc/intel/apollolake/cpu.c
+++ b/src/soc/intel/apollolake/cpu.c
@@ -54,7 +54,7 @@
REG_MSR_WRITE(MSR_PMG_IO_CAPTURE_BASE,
(ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))),
/* Disable support for MONITOR and MWAIT instructions */
- REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0),
+ REG_MSR_RMW(IA32_MISC_ENABLE, ~MONITOR_MWAIT_DIS_MASK, 0),
#endif
/* Disable C1E */
REG_MSR_RMW(MSR_POWER_CTL, ~POWER_CTL_C1E_MASK, 0),
diff --git a/src/soc/intel/baytrail/include/soc/msr.h b/src/soc/intel/baytrail/include/soc/msr.h
index fa0c40a..dd60345 100644
--- a/src/soc/intel/baytrail/include/soc/msr.h
+++ b/src/soc/intel/baytrail/include/soc/msr.h
@@ -23,7 +23,6 @@
#define MSR_POWER_MISC 0x120
#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
-#define MSR_IA32_MISC_ENABLES 0x1a0
#define MSR_POWER_CTL 0x1fc
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c
index 0aee1d7..f9c3014 100644
--- a/src/soc/intel/baytrail/tsc_freq.c
+++ b/src/soc/intel/baytrail/tsc_freq.c
@@ -60,9 +60,9 @@
msr_t msr;
/* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
* the PERF_CTL. */
diff --git a/src/soc/intel/braswell/include/soc/msr.h b/src/soc/intel/braswell/include/soc/msr.h
index 207a27d..ec0cbe3 100644
--- a/src/soc/intel/braswell/include/soc/msr.h
+++ b/src/soc/intel/braswell/include/soc/msr.h
@@ -24,7 +24,6 @@
#define MSR_POWER_MISC 0x120
#define ENABLE_ULFM_AUTOCM_MASK (1 << 2)
#define ENABLE_INDP_AUTOCM_MASK (1 << 3)
-#define MSR_IA32_MISC_ENABLES 0x1a0
#define MSR_POWER_CTL 0x1fc
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
diff --git a/src/soc/intel/braswell/tsc_freq.c b/src/soc/intel/braswell/tsc_freq.c
index de82e23..72dbca5 100644
--- a/src/soc/intel/braswell/tsc_freq.c
+++ b/src/soc/intel/braswell/tsc_freq.c
@@ -67,14 +67,14 @@
msr_t msr;
/* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Enable Burst Mode */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.hi = 0;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/*
* Set guranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 5e32e15..437aef0 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -29,7 +29,6 @@
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index 13276a6..0ceef9a 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -45,9 +45,6 @@
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
-#define IA32_MISC_ENABLE 0x1a0
-/* This is burst mode BIT 38 in MSR_IA32_MISC_ENABLES MSR at offset 1A0h */
-#define BURST_MODE_DISABLE (1 << 6)
#define MSR_TEMPERATURE_TARGET 0x1a2
#define MSR_PREFETCH_CTL 0x1a4
#define PREFETCH_L1_DISABLE (1 << 0)
diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c
index b7b5550..676fab7 100644
--- a/src/soc/intel/denverton_ns/cpu.c
+++ b/src/soc/intel/denverton_ns/cpu.c
@@ -44,9 +44,9 @@
/* Enable speed step. */
if (get_turbo_state() == TURBO_ENABLED) {
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= SPEED_STEP_ENABLE_BIT;
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
}
}
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index cc87871..d63cc04 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -31,7 +31,6 @@
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
#define FLEX_RATIO_EN (1 << 16)
-#define IA32_MISC_ENABLE 0x1a0
#define MSR_MISC_PWR_MGMT 0x1aa
#define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0)
#define MSR_TURBO_RATIO_LIMIT 0x1ad
diff --git a/src/soc/intel/fsp_baytrail/include/soc/msr.h b/src/soc/intel/fsp_baytrail/include/soc/msr.h
index e6143ae..6a2ce1a 100644
--- a/src/soc/intel/fsp_baytrail/include/soc/msr.h
+++ b/src/soc/intel/fsp_baytrail/include/soc/msr.h
@@ -20,7 +20,6 @@
#define MSR_PLATFORM_INFO 0xce
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
#define MSR_POWER_MISC 0x120
-#define MSR_IA32_MISC_ENABLES 0x1a0
#define MSR_POWER_CTL 0x1fc
#define MSR_PKG_POWER_SKU_UNIT 0x606
#define MSR_PKG_POWER_LIMIT 0x610
diff --git a/src/soc/intel/fsp_baytrail/tsc_freq.c b/src/soc/intel/fsp_baytrail/tsc_freq.c
index 0aee1d7..f9c3014 100644
--- a/src/soc/intel/fsp_baytrail/tsc_freq.c
+++ b/src/soc/intel/fsp_baytrail/tsc_freq.c
@@ -60,9 +60,9 @@
msr_t msr;
/* Enable speed step. */
- msr = rdmsr(MSR_IA32_MISC_ENABLES);
+ msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 16);
- wrmsr(MSR_IA32_MISC_ENABLES, msr);
+ wrmsr(IA32_MISC_ENABLE, msr);
/* Set guaranteed ratio [21:16] from IACORE_RATIOS to bits [15:8] of
* the PERF_CTL. */
To view, visit change 28855. To unsubscribe, or for help writing mail filters, visit settings.