Hannah Williams (hannah.williams@intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15056
-gerrit
commit 5cdad5d533d6b8281b934f609014894b2395e286 Author: Hannah Williams hannah.williams@intel.com Date: Thu Jun 2 15:00:36 2016 -0700
board/intel/amenia: Enable LPSS S0ix
This setting will enable S0ix for LPSS
Change-Id: Ie07cb8437d0cee61a03638aa980fd3322fef0c4e Signed-off-by: Hannah Williams hannah.williams@intel.com --- src/mainboard/intel/amenia/devicetree.cb | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/src/mainboard/intel/amenia/devicetree.cb b/src/mainboard/intel/amenia/devicetree.cb index 2080d6f..7045f59 100644 --- a/src/mainboard/intel/amenia/devicetree.cb +++ b/src/mainboard/intel/amenia/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/apollolake # 0x1A[6:0] stands for 26*125 = 3250 pSec delay for SDR104/HS200 register "emmc_tx_data_cntl1" = "0x1A1A" # HS400 required
+ # LPSS S0ix Enable + register "lpss_s0ix_enable" = "1" + device domain 0 on device pci 00.0 on end # - Host Bridge device pci 00.1 on end # - DPTF