Erin Lo has uploaded this change for review.
google/kukui: boot up sspm
Load sspm firmware form cbfs and bring up it.
BUG=b:80501386
BRANCH=none
Test=Boots correctly on Kukui.
Change-Id: I4ae6034454326f5115cd3948819adc448b67fb1c
Signed-off-by: Erin Lo <erin.lo@mediatek.com>
---
M src/mainboard/google/kukui/Kconfig
M src/mainboard/google/kukui/Makefile.inc
M src/mainboard/google/kukui/mainboard.c
M src/soc/mediatek/mt8183/Makefile.inc
M src/soc/mediatek/mt8183/include/soc/addressmap.h
A src/soc/mediatek/mt8183/include/soc/sspm.h
A src/soc/mediatek/mt8183/sspm.c
7 files changed, 94 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/31516/1
diff --git a/src/mainboard/google/kukui/Kconfig b/src/mainboard/google/kukui/Kconfig
index 9f477e5..0dcdb20 100644
--- a/src/mainboard/google/kukui/Kconfig
+++ b/src/mainboard/google/kukui/Kconfig
@@ -65,4 +65,8 @@
default "KUKUI TEST 9847" if BOARD_GOOGLE_KUKUI
default "FLAPJACK TEST 4147" if BOARD_GOOGLE_FLAPJACK
+config SSPM_BIN_FILE
+ string "SSPM BIN FILE"
+ default ""
+
endif
diff --git a/src/mainboard/google/kukui/Makefile.inc b/src/mainboard/google/kukui/Makefile.inc
index a0556c1..565c3f7 100644
--- a/src/mainboard/google/kukui/Makefile.inc
+++ b/src/mainboard/google/kukui/Makefile.inc
@@ -25,3 +25,8 @@
ramstage-y += mainboard.c
ramstage-y += memlayout.ld
ramstage-y += reset.c
+
+cbfs-files-y += sspm
+sspm-file := $(call strip_quotes,$(CONFIG_SSPM_BIN_FILE))
+sspm-type := raw
+sspm-compression :=$(CBFS_COMPRESS_FLAG)
diff --git a/src/mainboard/google/kukui/mainboard.c b/src/mainboard/google/kukui/mainboard.c
index e1d8f5f..5aaab8b 100644
--- a/src/mainboard/google/kukui/mainboard.c
+++ b/src/mainboard/google/kukui/mainboard.c
@@ -13,10 +13,13 @@
* GNU General Public License for more details.
*/
+#include <console/console.h>
+#include <cbfs.h>
#include <device/device.h>
#include <soc/gpio.h>
#include <soc/mmu_operations.h>
#include <soc/usb.h>
+#include <soc/sspm.h>
static void configure_emmc(void)
{
@@ -37,10 +40,29 @@
setup_usb_host();
}
+#define BUF_SIZE (64 * KiB)
+unsigned char buf[BUF_SIZE];
+
+static void sspm_boot(void)
+{
+ size_t fw_size = cbfs_boot_load_file("sspm", buf, sizeof(buf),
+ CBFS_TYPE_RAW);
+
+ if (fw_size == 0)
+ printk(BIOS_DEBUG, "no sspm\n");
+ else
+ printk(BIOS_DEBUG, "sspm[0]=%#x, [%zd]=%#x\n",
+ buf[0], fw_size - 1, buf[fw_size - 1]);
+
+ sspm_init(buf, BUF_SIZE);
+
+}
+
static void mainboard_init(struct device *dev)
{
configure_emmc();
configure_usb();
+ sspm_boot();
}
static void mainboard_enable(struct device *dev)
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc
index 5770a83..199b22d 100644
--- a/src/soc/mediatek/mt8183/Makefile.inc
+++ b/src/soc/mediatek/mt8183/Makefile.inc
@@ -49,6 +49,7 @@
ramstage-y += ../common/uart.c
ramstage-y += ../common/usb.c
ramstage-y += ../common/wdt.c
+ramstage-y += sspm.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include
CPPFLAGS_common += -Isrc/soc/mediatek/common/include
diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h
index d41b2b9..f812224 100644
--- a/src/soc/mediatek/mt8183/include/soc/addressmap.h
+++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h
@@ -34,6 +34,7 @@
EMI_BASE = IO_PHYS + 0x00219000,
EMI_MPU_BASE = IO_PHYS + 0x00226000,
DRAMC_CH_BASE = IO_PHYS + 0x00228000,
+ SSPM_BASE = IO_PHYS + 0x00440000,
AUXADC_BASE = IO_PHYS + 0x01001000,
UART0_BASE = IO_PHYS + 0x01002000,
SPI0_BASE = IO_PHYS + 0x0100A000,
diff --git a/src/soc/mediatek/mt8183/include/soc/sspm.h b/src/soc/mediatek/mt8183/include/soc/sspm.h
new file mode 100644
index 0000000..f006ca2
--- /dev/null
+++ b/src/soc/mediatek/mt8183/include/soc/sspm.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_MEDIATEK_MT8183_SSPM_H
+#define SOC_MEDIATEK_MT8183_SSPM_H
+
+#include <soc/addressmap.h>
+#include <types.h>
+
+struct mt8183_sspm_regs {
+ u32 sw_rstn;
+};
+static struct mt8183_sspm_regs *const mt8183_sspm = (void *)SSPM_BASE;
+#define CFG_SSPM_SRAM 0x10400000
+s32 sspm_init(unsigned char *buf, int len);
+#endif /* SOC_MEDIATEK_MT8183_SSPM_H */
diff --git a/src/soc/mediatek/mt8183/sspm.c b/src/soc/mediatek/mt8183/sspm.c
new file mode 100644
index 0000000..a42a0f5
--- /dev/null
+++ b/src/soc/mediatek/mt8183/sspm.c
@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2019 MediaTek Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/barrier.h>
+#include <arch/io.h>
+#include <soc/gpio.h>
+#include <soc/sspm.h>
+#include <string.h>
+
+#define SSPM_UART 1
+s32 sspm_init(unsigned char *buf, int len)
+{
+ memcpy((void*)CFG_SSPM_SRAM, buf, len);
+#if SSPM_UART
+ gpio_set_mode(GPIO(EINT4), PAD_EINT4_FUNC_SSPM_UTXD_AO);
+ gpio_set_mode(GPIO(EINT5), PAD_EINT5_FUNC_SSPM_URXD_AO);
+#endif
+ mb();
+ write32(&mt8183_sspm->sw_rstn, 0x1);
+ return 0;
+}
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