Patch Set 12:

I have recently noticed that after apu2 migration to postcar the MTRRs became inconsistent across all cores. The APs have an additional UC entry probably for cbmem?, which stays programmed up to the CPU init in ramstage. Since the postcar frame is built only from WB entries, the BSP has one entry less than APs which causes this inconsistence. Would this patch resolve this issue? Or is this something different?

Anyway I will test this.

Inconsistent MTRR is acceptable for a short amount of time like during the firmware. If the MTRRs are still incosistent when Linux boots that generally results in hangs.

Postcar (which is in dmar/cbmem) invalidates cache so it must hit dram before that. Making cbmem UC makes that possible but CLFLUSHing it to RAM (if possible) is a cleaner solution. It might also result in (small) boot speedups. This patch would indeed avoid making an UC MTRR 'hole' for cbmem.

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Iaa0d154e2c5b2052027d07ad26e31f3ff63ae9f3
Gerrit-Change-Number: 37197
Gerrit-PatchSet: 12
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Angel Pons <>
Gerrit-Reviewer: Michał Żygowski <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Paul Menzel <>
Gerrit-Comment-Date: Tue, 10 Nov 2020 14:32:04 +0000
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