Arthur Heymans has uploaded this change for review.
[WIP]mb/intel/minnowmax: Add mainboard
TODO: Fixup SPD handling, Check PCI (vendor disables most)
Working: USB (EHCI and XHCI), SATA, UART, ethernet
Change-Id: I9a1236425c8a0914f92adcad445230ef2692393a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
A src/mainboard/intel/minnowmax/Kconfig
A src/mainboard/intel/minnowmax/Kconfig.name
A src/mainboard/intel/minnowmax/Makefile.inc
A src/mainboard/intel/minnowmax/acpi/ec.asl
A src/mainboard/intel/minnowmax/acpi/mainboard.asl
A src/mainboard/intel/minnowmax/acpi/superio.asl
A src/mainboard/intel/minnowmax/acpi_tables.c
A src/mainboard/intel/minnowmax/board_info.txt
A src/mainboard/intel/minnowmax/cmos.layout
A src/mainboard/intel/minnowmax/data.vbt
A src/mainboard/intel/minnowmax/devicetree.cb
A src/mainboard/intel/minnowmax/dsdt.asl
A src/mainboard/intel/minnowmax/gpio.c
A src/mainboard/intel/minnowmax/irqroute.c
A src/mainboard/intel/minnowmax/irqroute.h
A src/mainboard/intel/minnowmax/mainboard.c
A src/mainboard/intel/minnowmax/romstage.c
A src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
M src/soc/intel/baytrail/Makefile.inc
M src/soc/intel/baytrail/refcode.c
20 files changed, 662 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44102/1
diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
new file mode 100644
index 0000000..d7ad307
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/Kconfig
@@ -0,0 +1,50 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+## Copyright (C) 2014 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+if BOARD_INTEL_MINNOWMAX
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select SOC_INTEL_BAYTRAIL
+ select BOARD_ROMSIZE_KB_8192
+ select HAVE_ACPI_TABLES
+ select HAVE_OPTION_TABLE
+ select ENABLE_BUILTIN_COM1 if CONSOLE_SERIAL
+ select HAVE_ACPI_RESUME
+ select INTEL_GMA_HAVE_VBT
+
+config MAINBOARD_DIR
+ string
+ default "intel/minnowmax"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "Minnow Max"
+
+config CBFS_SIZE
+ hex
+ default 0x00300000
+
+config POST_DEVICE
+ bool
+ default n
+
+config SEABIOS_HARDWARE_IRQ
+ bool
+ default n
+
+
+endif # BOARD_INTEL_MINNOWMAX
diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name
new file mode 100644
index 0000000..abe9225
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_MINNOWMAX
+ bool "Minnow Max"
diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc
new file mode 100644
index 0000000..6d22cdf
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/Makefile.inc
@@ -0,0 +1,22 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+ramstage-y += gpio.c
+ramstage-y += irqroute.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = micron_2GiB_dimm_MT41K256M16HA-125
+
+SPD_DEPS := $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex)
+
+# Include spd ROM data
+$(SPD_BIN): $(SPD_DEPS)
+ for f in $+; \
+ do for c in $$(cat $$f | grep -v ^#); \
+ do printf $$(printf '\%o' 0x$$c); \
+ done; \
+ done > $@
+
+cbfs-files-y += spd.bin
+spd.bin-file := $(SPD_BIN)
+spd.bin-type := spd
diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/acpi/ec.asl
diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl
new file mode 100644
index 0000000..d17d26f
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * NOTE: this has to be here even when the board has no LPE audio, otherwise
+ * it breaks the SOC specific ACPI code
+ */
+Scope (\_SB.PCI0.LPEA)
+{
+ Name (GBUF, ResourceTemplate () {})
+}
+
+
+Device (PWRB)
+{
+ Name(_HID, EisaId("PNP0C0C"))
+}
diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/acpi/superio.asl
diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c
new file mode 100644
index 0000000..5439050
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/acpi_tables.c
@@ -0,0 +1,44 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <acpi/acpi_gnvs.h>
+#include <arch/ioapic.h>
+#include <device/device.h>
+#include <soc/acpi.h>
+#include <soc/nvs.h>
+#include <soc/iomap.h>
+
+void acpi_create_gnvs(struct global_nvs *gnvs)
+{
+ acpi_init_gnvs(gnvs);
+
+ /* Enable USB ports in S3 */
+ gnvs->s3u0 = 1;
+ gnvs->s3u1 = 1;
+ /* Disable USB ports in S5 */
+ gnvs->s5u0 = 0;
+ gnvs->s5u1 = 0;
+ /* TPM not present */
+ gnvs->tpmp = 0;
+ /* Disable DPTF */
+ gnvs->dpte = 0;
+}
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ /* Local APICs */
+ current = acpi_create_madt_lapics(current);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
+ 2, IO_APIC_ADDR, 0);
+
+ current = acpi_madt_irq_overrides(current);
+
+ return current;
+}
+
+void mainboard_fill_fadt(acpi_fadt_t *fadt)
+{
+ fadt->preferred_pm_profile = PM_DESKTOP;
+}
diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt
new file mode 100644
index 0000000..5af79f8
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/board_info.txt
@@ -0,0 +1,4 @@
+Category: sbc
+ROM protocol: SPI
+Flashrom support: y
+Release year: 2014
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
new file mode 100644
index 0000000..bbc3f3c
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/cmos.layout
@@ -0,0 +1,44 @@
+
+## SPDX-License-Identifier: GPL-2.0-only
+# -----------------------------------------------------------------
+entries
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+388 4 h 0 reboot_counter
+# -----------------------------------------------------------------
+# coreboot config options: console
+395 4 e 6 debug_level
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 2 e 7 power_on_after_fail
+# coreboot config options: check sums
+984 16 h 0 check_sum
+# -----------------------------------------------------------------
+enumerations
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+6 0 Emergency
+6 1 Alert
+6 2 Critical
+6 3 Error
+6 4 Warning
+6 5 Notice
+6 6 Info
+6 7 Debug
+6 8 Spew
+7 0 Disable
+7 1 Enable
+7 2 Keep
+# -----------------------------------------------------------------
+checksums
+checksum 392 415 984
diff --git a/src/mainboard/intel/minnowmax/data.vbt b/src/mainboard/intel/minnowmax/data.vbt
new file mode 100644
index 0000000..cfb393c
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/data.vbt
Binary files differ
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
new file mode 100644
index 0000000..7f5a907
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/devicetree.cb
@@ -0,0 +1,82 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
+## Copyright (C) 2014 Intel Corporation
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+
+chip soc/intel/baytrail
+
+ register "usb2_comp_bg" = "0x4700"
+ # Allow PCIe devices to wake system from suspend
+ register "pcie_wake_enable" = "1"
+ # SATA port enable mask (2 ports)
+ register "sata_port_map" = "0x1"
+ register "sata_ahci" = "0x1"
+ # Do not route USB ports to XHCI
+ register "usb_route_to_xhci" = "0"
+ # USB Port Disable Mask
+ register "usb2_port_disable_mask" = "0x0"
+ register "usb3_port_disable_mask" = "0x0"
+ # USB PHY settings
+ register "usb2_per_port_lane0" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
+ register "usb2_per_port_lane1" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
+ register "usb2_per_port_lane2" = "0x00049209"
+ register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
+ register "usb2_per_port_lane3" = "0x00049a09"
+ register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
+ # Disable SLP_X stretching after SUS power well fail.
+ register "disable_slp_x_stretch_sus_fail" = "1"
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # 8086 0F00 - SoC router -
+ device pci 02.0 on end # 8086 0F31 - GFX micro HDMI
+ device pci 03.0 off end # 8086 0F38 - MIPI -
+
+ device pci 10.0 off end # 8086 0F14 - MMC Port -
+ device pci 11.0 off end # 8086 0F15 - SDIO Port -
+ device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3
+ device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC
+ device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
+ device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC
+ device pci 17.0 off end # 8086 0F50 - MMC45 Port -
+ device pci 18.0 on end # 8086 0F40 - SIO - DMA -
+ device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) -
+ device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints)
+ device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) -
+ device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) -
+ device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) -
+ device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC
+ device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC
+ device pci 1a.0 on end # 8086 0F18 - TXE -
+ device pci 1b.0 off end # 8086 0F04 - HD Audio -
+ device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on
+ device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models)
+ device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE
+ device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC
+ device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
+ device pci 1e.0 on end # 8086 0F06 - SIO - DMA -
+ device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC
+ device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC
+ device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC
+ device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC
+ device pci 1e.5 on end # 8086 0F0E - SPI LSEC
+ device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector
+ device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC
+ end
+end
diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl
new file mode 100644
index 0000000..0ae74495
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/dsdt.asl
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <acpi/acpi.h>
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ 0x02, // DSDT revision: ACPI v2.0 and up
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/baytrail/acpi/platform.asl>
+ // global NVS and variables
+ #include <soc/intel/baytrail/acpi/globalnvs.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+ Device (\_SB.PCI0)
+ {
+ #include <soc/intel/baytrail/acpi/southcluster.asl>
+ }
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+ #include "acpi/mainboard.asl"
+}
\ No newline at end of file
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
new file mode 100644
index 0000000..8b5a639
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/gpio.c
@@ -0,0 +1,242 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google Inc.
+ * Copyright (C) 2014 Sage Electronic Engineering, LLC.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdlib.h>
+#include <soc/gpio.h>
+#include "irqroute.h"
+
+#define GPIO_OUT_HIGH_LEGACY \
+ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \
+ .pad_conf1 = PAD_CONFIG1_DEFAULT, \
+ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \
+ .use_sel = GPIO_USE_LEGACY, \
+ .io_sel = GPIO_DIR_OUTPUT, \
+ .gp_lvl = GPIO_LEVEL_HIGH, \
+ .is_gpio = 1 }
+
+
+/*
+ * For multiplexed functions, look in EDS:
+ * 10.3 Ball Name and Function by Location
+ *
+ * The pads list is in the BWG_VOL2 Rev1p2:
+ * Note that Pad # is not the same as GPIO#
+ * 37 GPIO Handling:
+ * Table 37-1. SCORE Pads List
+ * Table 37-2. SSUSORE Pads List
+ */
+
+/* NCORE GPIOs */
+static const struct soc_gpio_map gpncore_gpio_map[] = {
+ GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD
+ GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT
+ GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK
+ GPIO_NC, // GPIO_S0_NC[03] - No Connect
+ GPIO_NC, // GPIO_S0_NC[04] - No Connect
+ GPIO_NC, // GPIO_S0_NC[05] - No Connect
+ GPIO_NC, // GPIO_S0_NC[06] - No Connect
+ GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT
+ GPIO_NC, // GPIO_S0_NC[08] - No Connect
+ GPIO_NC, // GPIO_S0_NC[09] - No Connect
+ GPIO_NC, // GPIO_S0_NC[10] - No Connect
+ GPIO_NC, // GPIO_S0_NC[11] - No Connect
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15
+ GPIO_NC, // GPIO_S0_NC[13] - No Connect
+ GPIO_NC, // GPIO_S0_NC[14] - No Connect
+ GPIO_NC, // GPIO_S0_NC[15] - No Connect
+ GPIO_NC, // GPIO_S0_NC[16] - No Connect
+ GPIO_NC, // GPIO_S0_NC[17] - No Connect
+ GPIO_NC, // GPIO_S0_NC[18] - No Connect
+ GPIO_NC, // GPIO_S0_NC[19] - No Connect
+ GPIO_NC, // GPIO_S0_NC[20] - No Connect
+ GPIO_NC, // GPIO_S0_NC[21] - No Connect
+ GPIO_NC, // GPIO_S0_NC[22] - No Connect
+ GPIO_NC, // GPIO_S0_NC[23] - No Connect
+ GPIO_NC, // GPIO_S0_NC[24] - No Connect
+ GPIO_NC, // GPIO_S0_NC[25] - No Connect
+ GPIO_NC, // GPIO_S0_NC[26] - No Connect
+ GPIO_END
+};
+
+/* SCORE GPIOs (GPIO_S0_SC_XX) */
+static const struct soc_gpio_map gpscore_gpio_map[] = {
+ GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0
+ GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1
+ GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B
+ GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0
+ GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1
+ GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2
+ GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3
+ GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP
+ GPIO_NC, // GPIO_S0_SC[008] - No Connect
+ GPIO_NC, // GPIO_S0_SC[009] - No Connect
+ GPIO_NC, // GPIO_S0_SC[010] - No Connect
+ GPIO_NC, // GPIO_S0_SC[011] - No Connect
+ GPIO_NC, // GPIO_S0_SC[012] - No Connect
+ GPIO_NC, // GPIO_S0_SC[013] - No Connect
+ GPIO_NC, // GPIO_S0_SC[014] - No Connect
+ GPIO_NC, // GPIO_S0_SC[015] - No Connect
+ GPIO_NC, // GPIO_S0_SC[016] - No Connect
+ GPIO_NC, // GPIO_S0_SC[017] - No Connect
+ GPIO_NC, // GPIO_S0_SC[018] - No Connect
+ GPIO_NC, // GPIO_S0_SC[019] - No Connect
+ GPIO_NC, // GPIO_S0_SC[020] - No Connect
+ GPIO_NC, // GPIO_S0_SC[021] - No Connect
+ GPIO_NC, // GPIO_S0_SC[022] - No Connect
+ GPIO_NC, // GPIO_S0_SC[023] - No Connect
+ GPIO_NC, // GPIO_S0_SC[024] - No Connect
+ GPIO_NC, // GPIO_S0_SC[025] - No Connect
+ GPIO_NC, // GPIO_S0_SC[026] - No Connect
+ GPIO_NC, // GPIO_S0_SC[027] - No Connect
+ GPIO_NC, // GPIO_S0_SC[028] - No Connect
+ GPIO_NC, // GPIO_S0_SC[029] - No Connect
+ GPIO_NC, // GPIO_S0_SC[030] - No Connect
+ GPIO_NC, // GPIO_S0_SC[031] - No Connect
+ GPIO_NC, // GPIO_S0_SC[032] - No Connect
+ GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK
+ GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0
+ GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1
+ GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2
+ GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3
+ GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD#
+ GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD
+ GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN)
+ GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN)
+ GPIO_NC, // GPIO_S0_SC[042] - No Connect
+ GPIO_NC, // GPIO_S0_SC[043] - No Connect
+ GPIO_NC, // GPIO_S0_SC[044] - No Connect
+ GPIO_NC, // GPIO_S0_SC[045] - No Connect
+ GPIO_NC, // GPIO_S0_SC[046] - No Connect
+ GPIO_NC, // GPIO_S0_SC[047] - No Connect
+ GPIO_NC, // GPIO_S0_SC[048] - No Connect
+ GPIO_NC, // GPIO_S0_SC[049] - No Connect
+ GPIO_NC, // GPIO_S0_SC[050] - No Connect
+ GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA
+ GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK
+ GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT
+ GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55)
+ GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56
+ GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58)
+ GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB
+ GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB
+ GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD
+ GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK
+ GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM
+ GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN
+ GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT
+ GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1
+ GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO
+ GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI
+ GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK
+ GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD
+ GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD
+ GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB
+ GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB
+ GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD
+ GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD
+ GPIO_NC, // GPIO_S0_SC[076] - No Connect
+ GPIO_NC, // GPIO_S0_SC[077] - No Connect
+ GPIO_NC, // GPIO_S0_SC[078] - No Connect
+ GPIO_NC, // GPIO_S0_SC[079] - No Connect
+ GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA)
+ GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL)
+ GPIO_NC, // GPIO_S0_SC[082] - No Connect
+ GPIO_NC, // GPIO_S0_SC[083] - No Connect
+ GPIO_NC, // GPIO_S0_SC[084] - No Connect
+ GPIO_NC, // GPIO_S0_SC[085] - No Connect
+ GPIO_NC, // GPIO_S0_SC[086] - No Connect
+ GPIO_NC, // GPIO_S0_SC[087] - No Connect
+ GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA
+ GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL
+ GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA
+ GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL
+ GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13
+ GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16
+ GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0
+ GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1
+ GPIO_NC, // GPIO_S0_SC[096] - No Connect
+ GPIO_NC, // GPIO_S0_SC[097] - No Connect
+ GPIO_NC, // GPIO_S0_SC[098] - No Connect
+ GPIO_NC, // GPIO_S0_SC[099] - No Connect
+ GPIO_NC, // GPIO_S0_SC[100] - No Connect
+ GPIO_NC, // GPIO_S0_SC[101] - No Connect
+ GPIO_END
+};
+
+/* SSUS GPIOs (GPIO_S5) */
+static const struct soc_gpio_map gpssus_gpio_map[] = {
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2
+ GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB
+ GPIO_NC, // GPIO_S5[04] - No Connect
+ GPIO_INPUT, // GPIO_S5[05] - BOM_OP1
+ // Memory: 0=1GB 1=2GB or 4GB
+ GPIO_INPUT, // GPIO_S5[06] - BOM_OP2
+ GPIO_INPUT, // GPIO_S5[07] - BOM_OP3
+ GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0
+ GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1
+ GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK
+ GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14)
+ GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0
+ GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10)
+ GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20
+ GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R
+ GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN
+ GPIO_NC, // GPIO_S5[17] - No Connect
+ GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7)
+ GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0
+ GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1
+ GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B
+ GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3
+ GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4
+ GPIO_NC, // GPIO_S5[31] - No Connect
+ GPIO_NC, // GPIO_S5[32] - No Connect
+ GPIO_NC, // GPIO_S5[33] - No Connect
+ GPIO_NC, // GPIO_S5[34] - No Connect
+ GPIO_NC, // GPIO_S5[35] - No Connect
+ GPIO_NC, // GPIO_S5[36] - No Connect
+ GPIO_NC, // GPIO_S5[37] - No Connect
+ GPIO_NC, // GPIO_S5[38] - No Connect
+ GPIO_NC, // GPIO_S5[39] - No Connect
+ GPIO_NC, // GPIO_S5[40] - No Connect
+ GPIO_NC, // GPIO_S5[41] - No Connect
+ GPIO_NC, // GPIO_S5[42] - No Connect
+ GPIO_NC, // GPIO_S5[43] - No Connect
+ GPIO_END
+};
+
+static struct soc_gpio_config gpio_config = {
+ .ncore = gpncore_gpio_map,
+ .score = gpscore_gpio_map,
+ .ssus = gpssus_gpio_map,
+ .core_dirq = NULL,
+ .sus_dirq = NULL,
+};
+
+struct soc_gpio_config *mainboard_get_gpios(void)
+{
+ return &gpio_config;
+}
diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c
new file mode 100644
index 0000000..6fa0366
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/irqroute.c
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include "irqroute.h"
+
+DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h
new file mode 100644
index 0000000..e0e43f0
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/irqroute.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <soc/irq.h>
+#include <soc/pci_devs.h>
+
+#define PCI_DEV_PIRQ_ROUTES \
+ PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SD_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, B, C, D), \
+ PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D)
+
+#define PIRQ_PIC_ROUTES \
+ PIRQ_PIC(A, DISABLE), \
+ PIRQ_PIC(B, DISABLE), \
+ PIRQ_PIC(C, DISABLE), \
+ PIRQ_PIC(D, DISABLE), \
+ PIRQ_PIC(E, DISABLE), \
+ PIRQ_PIC(F, DISABLE), \
+ PIRQ_PIC(G, DISABLE), \
+ PIRQ_PIC(H, DISABLE)
diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c
new file mode 100644
index 0000000..69b9405
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/mainboard.c
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+#include <bootstate.h>
+void mainboard_suspend_resume(void)
+{
+}
+
+static void mainboard_init(struct device *dev)
+{
+}
+static int mainboard_smbios_data(struct device *dev, int *handle,
+ unsigned long *current)
+{
+ return 0;
+}
+// mainboard_enable is executed as first thing after
+// enumerate_buses().
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->init = mainboard_init;
+ dev->ops->get_smbios_data = mainboard_smbios_data;
+}
+struct chip_operations mainboard_ops = {
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
new file mode 100644
index 0000000..c504cd4
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/romstage.c
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <stdint.h>
+#include <soc/gpio.h>
+#include <cbfs.h>
+#include <console/console.h>
+#include <soc/mrc_wrapper.h>
+#include <soc/romstage.h>
+
+#define DRAM_GPIO_FUSE 5
+#define SPD_SIZE 256
+
+static void *get_spd_pointer(char *spd_file_content)
+{
+ u8 gpio5 = 0;
+
+ ssus_disable_internal_pull(DRAM_GPIO_FUSE);
+
+ gpio5 = ssus_get_gpio(DRAM_GPIO_FUSE);
+
+ // TODO
+ return &spd_file_content[SPD_SIZE * 0];
+}
+
+void mainboard_fill_mrc_params(struct mrc_params *mp)
+{
+ void *spd_content;
+ void *spd_file;
+ size_t spd_fsize;
+
+ spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_fsize);
+
+ if (!spd_file)
+ die("SPD data not found.");
+
+ spd_content = get_spd_pointer(spd_file);
+
+ mp->mainboard.dram_type = DRAM_DDR3L;
+ mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM;
+ mp->mainboard.weaker_odt_settings = 1;
+
+ mp->mainboard.dram_data[0] = spd_content;
+}
diff --git a/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
new file mode 100644
index 0000000..f3bcb56
--- /dev/null
+++ b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex
@@ -0,0 +1,32 @@
+92 11 0b 03 04 19 02 02
+03 11 01 08 0a 00 fe 00
+69 78 69 3c 69 11 18 86
+20 08 3c 3c 01 40 83 05
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 0f 01 02 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 80 2c 00
+00 00 00 00 00 00 19 d2
+34 4b 54 46 32 35 36 36
+34 48 5a 2d 31 47 36 45
+31 20 45 31 80 2c 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
+ff ff ff ff ff ff ff ff
diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc
index bfa1846..cd03458 100644
--- a/src/soc/intel/baytrail/Makefile.inc
+++ b/src/soc/intel/baytrail/Makefile.inc
@@ -66,8 +66,7 @@
postcar-y += ../../../cpu/intel/car/non-evict/exit_car.S
-cpu_microcode_bins += 3rdparty/blobs/soc/intel/baytrail/microcode.bin \
- 3rdparty/intel-microcode/intel-ucode/06-37-09
+cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-37-*
CPPFLAGS_common += -Isrc/soc/intel/baytrail/include
diff --git a/src/soc/intel/baytrail/refcode.c b/src/soc/intel/baytrail/refcode.c
index 297ed9c..99fb335 100644
--- a/src/soc/intel/baytrail/refcode.c
+++ b/src/soc/intel/baytrail/refcode.c
@@ -19,7 +19,7 @@
static efi_wrapper_entry_t load_refcode_from_cache(void)
{
- struct prog refcode;
+ static struct prog refcode;
printk(BIOS_DEBUG, "refcode loading from cache.\n");
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