Ana Carolina Cabral has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84917?usp=email )
Change subject: soc/amd/common/spi: Create header for SPI defines ......................................................................
soc/amd/common/spi: Create header for SPI defines
Move SPI defines to header file so they can be used in asl files.
Change-Id: I24de8c05a65c915bd4979d91bd1c2bfa6864b752 Signed-off-by: Ana Carolina Cabral ana.cpmelo95@gmail.com --- M src/soc/amd/common/block/include/amdblocks/spi.h A src/soc/amd/common/block/include/amdblocks/spi_defs.h 2 files changed, 64 insertions(+), 54 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/84917/1
diff --git a/src/soc/amd/common/block/include/amdblocks/spi.h b/src/soc/amd/common/block/include/amdblocks/spi.h index eafc2c2..535b261 100644 --- a/src/soc/amd/common/block/include/amdblocks/spi.h +++ b/src/soc/amd/common/block/include/amdblocks/spi.h @@ -6,8 +6,7 @@ #include <thread.h> #include <types.h>
-#define SPI_CNTRL0 0x00 -#define SPI_BUSY BIT(31) +#include "spi_defs.h"
enum spi_read_mode { SPI_READ_MODE_NORMAL33M = 0, @@ -19,28 +18,7 @@ SPI_READ_MODE_NORMAL66M = 6, SPI_READ_MODE_FAST_READ = 7, }; -/* - * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for - * SpiReadMode. - */ -#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) -#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) -#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) -#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ - SPI_READ_MODE_LOWER_BITS(x)) -#define SPI_ACCESS_MAC_ROM_EN BIT(22)
-#define SPI100_ENABLE 0x20 -#define SPI_USE_SPI100 BIT(0) - -#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) -#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) -#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) -#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ - DECODE_SPI_MODE_LOWER_BITS(x)) - -/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ -#define SPI100_SPEED_CONFIG 0x22 enum spi100_speed { SPI_SPEED_66M = 0, SPI_SPEED_33M = 1, @@ -50,37 +28,6 @@ SPI_SPEED_800K = 5, };
-#define SPI_SPEED_MASK 0xf -#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) -#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) -#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) -#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) -#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) - -#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ - SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) - -#define DECODE_SPEED_MASK 0x07 -#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) -#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) -#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) -#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) -#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) - -#define SPI100_HOST_PREF_CONFIG 0x2c -#define SPI_RD4DW_EN_HOST BIT(15) - -#define SPI_ROM_PAGE 0x5c - -#define SPI_FIFO 0x80 -#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ -#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) - -#define SPI_MISC_CNTRL 0xfc -/* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize - access to the SPI controller between SMM and non-SMM software/OS driver. */ -#define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4) - struct spi_config { /* * Default values if not overridden by mainboard: diff --git a/src/soc/amd/common/block/include/amdblocks/spi_defs.h b/src/soc/amd/common/block/include/amdblocks/spi_defs.h new file mode 100644 index 0000000..b9a06e3 --- /dev/null +++ b/src/soc/amd/common/block/include/amdblocks/spi_defs.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef AMD_BLOCK_SPI_DEFS_H +#define AMD_BLOCK_SPI_DEFS_H + +#define SPI_CNTRL0 0x00 +#define SPI_BUSY BIT(31) +/* + * SPI read mode is split into bits 18, 29, 30 such that [30:29:18] correspond to bits [2:0] for + * SpiReadMode. + */ +#define SPI_READ_MODE_MASK (BIT(30) | BIT(29) | BIT(18)) +#define SPI_READ_MODE_UPPER_BITS(x) ((((x) >> 1) & 0x3) << 29) +#define SPI_READ_MODE_LOWER_BITS(x) (((x) & 0x1) << 18) +#define SPI_READ_MODE(x) (SPI_READ_MODE_UPPER_BITS(x) | \ + SPI_READ_MODE_LOWER_BITS(x)) +#define SPI_ACCESS_MAC_ROM_EN BIT(22) + +#define SPI100_ENABLE 0x20 +#define SPI_USE_SPI100 BIT(0) + +#define DECODE_SPI_MODE_BITS(x) ((x) & SPI_READ_MODE_MASK) +#define DECODE_SPI_MODE_UPPER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 28) & 0x06) +#define DECODE_SPI_MODE_LOWER_BITS(x) ((DECODE_SPI_MODE_BITS(x) >> 18) & 0x01) +#define DECODE_SPI_READ_MODE(x) (DECODE_SPI_MODE_UPPER_BITS(x) | \ + DECODE_SPI_MODE_LOWER_BITS(x)) + +/* Use SPI_SPEED_16M-SPI_SPEED_66M below for the southbridge */ +#define SPI100_SPEED_CONFIG 0x22 + +#define SPI_SPEED_MASK 0xf +#define SPI_SPEED_MODE(x, shift) (((x) & SPI_SPEED_MASK) << shift) +#define SPI_NORM_SPEED(x) SPI_SPEED_MODE(x, 12) +#define SPI_FAST_SPEED(x) SPI_SPEED_MODE(x, 8) +#define SPI_ALT_SPEED(x) SPI_SPEED_MODE(x, 4) +#define SPI_TPM_SPEED(x) SPI_SPEED_MODE(x, 0) + +#define SPI_SPEED_CFG(n, f, a, t) (SPI_NORM_SPEED(n) | SPI_FAST_SPEED(f) | \ + SPI_ALT_SPEED(a) | SPI_TPM_SPEED(t)) + +#define DECODE_SPEED_MASK 0x07 +#define DECODE_SPEED_MODE(x, shift) (((x) >> shift) & DECODE_SPEED_MASK) +#define DECODE_SPI_NORMAL_SPEED(x) DECODE_SPEED_MODE(x, 12) +#define DECODE_SPI_FAST_SPEED(x) DECODE_SPEED_MODE(x, 8) +#define DECODE_SPI_ALT_SPEED(x) DECODE_SPEED_MODE(x, 4) +#define DECODE_SPI_TPM_SPEED(x) DECODE_SPEED_MODE(x, 0) + +#define SPI100_HOST_PREF_CONFIG 0x2c +#define SPI_RD4DW_EN_HOST BIT(15) + +#define SPI_ROM_PAGE 0x5c + +#define SPI_FIFO 0x80 +#define SPI_FIFO_LAST_BYTE 0xc6 /* 0xc7 for Cezanne */ +#define SPI_FIFO_DEPTH (SPI_FIFO_LAST_BYTE - SPI_FIFO + 1) + +#define SPI_MISC_CNTRL 0xfc +/* AMD has re-purposed this unused SPI controller register bit as a semaphore to synchronize + access to the SPI controller between SMM and non-SMM software/OS driver. */ +#define SPI_SEMAPHORE_DRIVER_LOCKED BIT(4) + + +#endif /* AMD_BLOCK_DATA_FABRIC_DEFS_H */