[coreboot-gerrit] Patch set updated for coreboot: nb/intel/i945/raminit.c: Refactor tRD selection

[Arthur Heymans]

Arthur Heymans ([e-mail]) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18354

-gerrit

commit 2ab2564611415ddc7bec9091eca0deee75c0fee9
Author: Arthur Heymans 
Date:   Sun Feb 12 23:34:39 2017 +0100

nb/intel/i945/raminit.c: Refactor tRD selection

Inspired by gm45 code, which sets this value the same way.

Some values for tRD on 800 and 1067MHz FSB were set wrong because the
    CAS/Freq selection was wrong.

PASSED memtest86+ during 10h+ on 1067MHZ fsb with 667MHz ddr2, CAS 5

Change-Id: I8002daf25b7603131b78b01075f43fd23747dd94
    Signed-off-by: Arthur Heymans 
---
 src/northbridge/intel/i945/raminit.c | 49 ++++++++++--------------------------
 1 file changed, 13 insertions(+), 36 deletions(-)

diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index cc227cc..782f4f0 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -1720,21 +1720,11 @@ static void sdram_program_odt_tristate(struct sys_info *sysinfo)

static void sdram_set_timing_and_control(struct sys_info *sysinfo)
 {
-	u32 reg32, off32;
+	u32 reg32, tRD_min;
    u32 tWTR;
    u32 temp_drt;
    int i, page_size;

-	static const u8 drt0_table[] = {
-	  /* CL 3, 4, 5 */
-		3, 4, 5,	/* FSB533, DDR667/533/400 */
-		4, 5, 6,	/* FSB667, DDR667/533/400 */
-		5, 6, 7,	/* FSB800, DDR400/533 */
-		6, 7, 8,	/* FSB800, DDR667 */
-		5, 6, 7,	/* FSB1066, DDR400 */
-		7, 8, 9,	/* FSB1066, DDR533/DDR667 */
-	};
-
    static const u8 cas_table[] = {
    	2, 1, 0, 3
    };
@@ -1787,34 +1777,21 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo)
    /* CxDRT0 [23:22], [21:20], [19:18] [16] have fixed values */
    temp_drt |= ( (1 << 22) | (3 << 20) | (1 << 18) | (0 << 16) );

-	/* Program Write Auto Precharge to Activate */
-	off32 = 0;
+	/*
+	 * tRD is the delay the memory controller is waiting on the FSB, 
+	 * in mclk domain.
+	 * This parameter is important for stability and performance.
+	 * Those values might not be optimal but seem stable.
+	 */
+	tRD_min = sysinfo->cas;
    switch (sysinfo->fsb_frequency) {
-	case 533:
-		off32 = 0;
-		break;
-	case 667:
-		off32 = 3;
-		break;
-	case 800:
-		if (sysinfo->memory_frequency <= 533) {
-			off32 = 6;
-			break;
-		}
-		off32 = 9;
-		break;
-	case 1066:
-		if (sysinfo->memory_frequency == 400) {
-			off32 = 12;
-			break;
-		}
-		off32 = 15;
-		break;
+	case 533: break;
+	case 667: tRD_min += 1; break;
+	case 800: tRD_min += 2; break;
+	case 1066: tRD_min += 3; break;
    }

-	off32 += sysinfo->cas - 3;
-	reg32 = drt0_table[off32];
-	temp_drt |= (reg32 << 11);
+	temp_drt |= (tRD_min << 11);

/* Read Auto Precharge to Activate */