Patrick Georgi merged this change.

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mb/google/hatch: Support 16MiB fmap

Add a fmd file for 16MiB fmap, so that we can support
both 16MiB / 32MiB SPI flash ROM chips.

BUG=b:129464811
TEST=build hatch firmware image with 16MiB fmap and
verify fmap is updated by 'fuility dump_fmap'

Change-Id: Ifc0103c7fd0d99439f40a31d23422401a6dce826
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
---
M src/mainboard/google/hatch/Kconfig
M src/mainboard/google/hatch/Kconfig.name
A src/mainboard/google/hatch/chromeos-16MiB.fmd
3 files changed, 50 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/hatch/Kconfig b/src/mainboard/google/hatch/Kconfig
index 041ac2d..63339f2 100644
--- a/src/mainboard/google/hatch/Kconfig
+++ b/src/mainboard/google/hatch/Kconfig
@@ -1,7 +1,6 @@
 
 config BOARD_GOOGLE_BASEBOARD_HATCH
 	def_bool n
-	select BOARD_ROMSIZE_KB_32768
 	select DRIVERS_GENERIC_GPIO_KEYS
 	select DRIVERS_GENERIC_MAX98357A
 	select DRIVERS_I2C_GENERIC
@@ -54,6 +53,11 @@
 config UART_FOR_CONSOLE
 	default 0
 
+config FMDFILE
+	string
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-16MiB.fmd" if BOARD_ROMSIZE_KB_16384
+	default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos.fmd" if BOARD_ROMSIZE_KB_32768
+
 config GBB_HWID
 	string
 	depends on CHROMEOS
diff --git a/src/mainboard/google/hatch/Kconfig.name b/src/mainboard/google/hatch/Kconfig.name
index edfa8e7..eb8e612 100644
--- a/src/mainboard/google/hatch/Kconfig.name
+++ b/src/mainboard/google/hatch/Kconfig.name
@@ -3,14 +3,17 @@
 config BOARD_GOOGLE_HATCH
 	bool "->  Hatch"
 	select BOARD_GOOGLE_BASEBOARD_HATCH
+	select BOARD_ROMSIZE_KB_32768
 	select SOC_INTEL_COMETLAKE
 
 config BOARD_GOOGLE_HATCH_WHL
 	bool "->  Hatch_whl"
 	select BOARD_GOOGLE_BASEBOARD_HATCH
+	select BOARD_ROMSIZE_KB_32768
 	select SOC_INTEL_WHISKEYLAKE
 
 config BOARD_GOOGLE_KOHAKU
 	bool "->  Kohaku"
 	select BOARD_GOOGLE_BASEBOARD_HATCH
+	select BOARD_ROMSIZE_KB_16384
 	select SOC_INTEL_COMETLAKE
diff --git a/src/mainboard/google/hatch/chromeos-16MiB.fmd b/src/mainboard/google/hatch/chromeos-16MiB.fmd
new file mode 100644
index 0000000..1594ab3
--- /dev/null
+++ b/src/mainboard/google/hatch/chromeos-16MiB.fmd
@@ -0,0 +1,42 @@
+FLASH@0xff000000 0x1000000 {
+	SI_ALL@0x0 0x400000 {
+		SI_DESC@0x0 0x1000
+		SI_ME@0x1000 0x3ff000
+	}
+	SI_BIOS@0x400000 0xc00000 {
+		RW_SECTION_A@0x0 0x380000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x36ffc0
+			RW_FWID_A@0x37ffc0 0x40
+		}
+		RW_SECTION_B@0x380000 0x380000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x36ffc0
+			RW_FWID_B@0x37ffc0 0x40
+		}
+		RW_MISC@0x700000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG(PRESERVE)@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD(PRESERVE)@0x28000 0x2000
+			RW_NVRAM(PRESERVE)@0x2a000 0x6000
+		}
+		RW_LEGACY(CBFS)@0x730000 0xd0000
+		WP_RO@0x800000 0x400000 {
+			RO_VPD(PRESERVE)@0x0 0x4000
+			RO_SECTION@0x4000 0x3fc000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x30c000
+			}
+		}
+	}
+}

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