HAOUAS Elyes has uploaded this change for review.

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ec/google/chromeec: Remove redundant use of ACPI offset operator

Change-Id: Iedf67f1caafa9627491e8b8f91be69b551d07ae8
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/ec/google/chromeec/acpi/ec.asl
M src/ec/google/chromeec/acpi/emem.asl
2 files changed, 0 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/32142/1

diff --git a/src/ec/google/chromeec/acpi/ec.asl b/src/ec/google/chromeec/acpi/ec.asl
index 962988e..b6c2231 100644
--- a/src/ec/google/chromeec/acpi/ec.asl
+++ b/src/ec/google/chromeec/acpi/ec.asl
@@ -41,7 +41,6 @@
 	OperationRegion (ERAM, EmbeddedControl, 0x00, EC_ACPI_MEM_MAPPED_BEGIN)
 	Field (ERAM, ByteAcc, Lock, Preserve)
 	{
-		Offset (0x00),
 		RAMV, 8,	// EC RAM Version
 		TSTB, 8,	// Test Byte
 		TSTC, 8,	// Complement of Test Byte
@@ -54,7 +53,6 @@
 		TBMD, 1,	// Tablet mode
 		DDPN, 3,	// Device DPTF Profile Number
 		// DFUD must be 0 for the other 31 values to be valid
-		Offset (0x0a),
 		DFUD, 1,	// Device Features Undefined
 		FLSH, 1,	// Flash commands present
 		PFAN, 1,	// PWM Fan control present
@@ -88,7 +86,6 @@
 		RWSG, 1,	// EC has RWSIG task enabled
 		DEVE, 1,	// EC supports device events
 		// make sure we're within our space envelope
-		Offset (0x0e),
 		Offset (0x12),
 		BTID, 8,	// Battery index that host wants to read
 		USPP, 8,	// USB Port Power
diff --git a/src/ec/google/chromeec/acpi/emem.asl b/src/ec/google/chromeec/acpi/emem.asl
index 982ec5b..77b4708 100644
--- a/src/ec/google/chromeec/acpi/emem.asl
+++ b/src/ec/google/chromeec/acpi/emem.asl
@@ -17,7 +17,6 @@
  * EMEM data may be accessed through port 62/66 or through LPC at 900h.
  */
 
-Offset (0x00),
 TIN0, 8,	// Temperature 0
 TIN1, 8,	// Temperature 1
 TIN2, 8,	// Temperature 2

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