Sugnan Prabhu S would like V Sowmya to review this change.
mb/intel/shadowmountain: Initial commit for Shadowmountain
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I781baa9143c1857c690297bc44c158f1335b313d
---
A src/mainboard/intel/shadowmountain/Kconfig
A src/mainboard/intel/shadowmountain/Kconfig.name
A src/mainboard/intel/shadowmountain/Makefile.inc
A src/mainboard/intel/shadowmountain/board_id.c
A src/mainboard/intel/shadowmountain/board_id.h
A src/mainboard/intel/shadowmountain/board_info.txt
A src/mainboard/intel/shadowmountain/bootblock.c
A src/mainboard/intel/shadowmountain/chromeos.c
A src/mainboard/intel/shadowmountain/chromeos.fmd
A src/mainboard/intel/shadowmountain/dsdt.asl
A src/mainboard/intel/shadowmountain/ec.c
A src/mainboard/intel/shadowmountain/mainboard.c
A src/mainboard/intel/shadowmountain/romstage.c
A src/mainboard/intel/shadowmountain/smihandler.c
A src/mainboard/intel/shadowmountain/spd/Makefile.inc
A src/mainboard/intel/shadowmountain/spd/adlrvp_lp5.spd.hex
A src/mainboard/intel/shadowmountain/spd/empty.spd.hex
A src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
A src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
A src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h
A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h
A src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
A src/mainboard/intel/shadowmountain/variants/baseboard/memory.c
A src/mainboard/intel/shadowmountain/variants/shadowmountain/overridetree.cb
25 files changed, 1,381 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/48455/1
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig
new file mode 100644
index 0000000..cd27b56
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/Kconfig
@@ -0,0 +1,74 @@
+if BOARD_INTEL_SHADOWMOUNTAIN
+
+config BOARD_SPECIFIC_OPTIONS
+ def_bool y
+ select BOARD_ROMSIZE_KB_32768
+ select DRIVERS_I2C_GENERIC
+ select DRIVERS_I2C_HID
+ select DRIVERS_INTEL_DPTF
+ select DRIVERS_INTEL_PMC
+ select DRIVERS_SPI_ACPI
+ select DRIVERS_USB_ACPI
+ select EC_GOOGLE_CHROMEEC
+ select EC_GOOGLE_CHROMEEC_BOARDID
+ select EC_GOOGLE_CHROMEEC_SKUID
+ select EC_GOOGLE_CHROMEEC_LPC
+ select HAVE_ACPI_RESUME
+ select HAVE_ACPI_TABLES
+ select INTEL_LPSS_UART_FOR_CONSOLE
+ select MAINBOARD_HAS_CHROMEOS
+# select MAINBOARD_HAS_SPI_TPM_CR50
+# select MAINBOARD_HAS_TPM2
+ select SOC_INTEL_ALDERLAKE
+ select HAVE_SPD_IN_CBFS
+
+config CHROMEOS
+ bool
+ default y
+ select GBB_FLAG_FORCE_DEV_SWITCH_ON
+ select GBB_FLAG_FORCE_DEV_BOOT_USB
+ select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
+ select GBB_FLAG_FORCE_MANUAL_RECOVERY
+ select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC
+
+config VBOOT
+ select EC_GOOGLE_CHROMEEC_SWITCHES
+ select VBOOT_LID_SWITCH
+ select VBOOT_MOCK_SECDATA
+ select HAS_RECOVERY_MRC_CACHE
+
+config DIMM_SPD_SIZE
+ int
+ default 512
+
+config DEVICETREE
+ string
+ default "variants/baseboard/devicetree.cb"
+
+config OVERRIDE_DEVICETREE
+ string
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
+
+#config DRIVER_TPM_SPI_BUS
+# default 0x1
+
+config MAINBOARD_DIR
+ string
+ default "intel/shadowmountain"
+
+config MAINBOARD_FAMILY
+ string
+ default "Shadow Mountain"
+
+config MAINBOARD_PART_NUMBER
+ string
+ default "shadowmountain"
+
+config TPM_TIS_ACPI_INTERRUPT
+ int
+ default 3 # GPE0_DW0_3 (GPP_C3)
+
+config VARIANT_DIR
+ string
+ default "shadowmountain"
+endif
diff --git a/src/mainboard/intel/shadowmountain/Kconfig.name b/src/mainboard/intel/shadowmountain/Kconfig.name
new file mode 100644
index 0000000..e489039
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_SHADOWMOUNTAIN
+ bool "shadowmountain"
diff --git a/src/mainboard/intel/shadowmountain/Makefile.inc b/src/mainboard/intel/shadowmountain/Makefile.inc
new file mode 100644
index 0000000..51683bc
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/Makefile.inc
@@ -0,0 +1,27 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage.c
+romstage-y += board_id.c
+
+smm-y += smihandler.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += ec.c
+ramstage-y += mainboard.c
+ramstage-y += board_id.c
+
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+VARIANT_DIR:=$(call strip_quotes,$(CONFIG_VARIANT_DIR))
+subdirs-y += variants/$(VARIANT_DIR)
+subdirs-y += variants/$(VARIANT_DIR)/memory
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
+
+subdirs-y += spd
diff --git a/src/mainboard/intel/shadowmountain/board_id.c b/src/mainboard/intel/shadowmountain/board_id.c
new file mode 100644
index 0000000..332ba1b
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/board_id.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdint.h>
+#include <types.h>
+#include "board_id.h"
+
+static uint32_t get_board_id_via_ext_ec(void)
+{
+ uint32_t id = BOARD_ID_INIT;
+
+ if (google_chromeec_get_board_version(&id))
+ id = BOARD_ID_UNKNOWN;
+
+ return id;
+}
+
+/* Get Board ID via EC I/O port write/read */
+int get_board_id(void)
+{
+ MAYBE_STATIC_NONZERO int id = -1;
+
+ if (id < 0) {
+ if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+ id = get_board_id_via_ext_ec();
+ } else {
+ if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+ id = recv_ec_data() << 8;
+ id |= recv_ec_data();
+ }
+ }
+ }
+ return (id & BOARD_ID_MASK);
+}
diff --git a/src/mainboard/intel/shadowmountain/board_id.h b/src/mainboard/intel/shadowmountain/board_id.h
new file mode 100644
index 0000000..2988127
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/board_id.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD 0x0d
+/* Bit 5:0 for Board ID */
+#define BOARD_ID_MASK 0x3f
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
diff --git a/src/mainboard/intel/shadowmountain/board_info.txt b/src/mainboard/intel/shadowmountain/board_info.txt
new file mode 100644
index 0000000..ff0fe2e
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Alderlake Pre-CEP Shadowmountain Board
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/shadowmountain/bootblock.c b/src/mainboard/intel/shadowmountain/bootblock.c
new file mode 100644
index 0000000..e2f914d
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/bootblock.c
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+
+void bootblock_mainboard_init(void)
+{
+ const struct pad_config *pads;
+ size_t num;
+
+ pads = variant_early_gpio_table(&num);
+ gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/intel/shadowmountain/chromeos.c b/src/mainboard/intel/shadowmountain/chromeos.c
new file mode 100644
index 0000000..ba4fd9c
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/chromeos.c
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+ struct lb_gpio chromeos_gpios[] = {
+ {-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+ {-1, ACTIVE_HIGH, 0, "power"},
+ {-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+ {GPIO_EC_IN_RW, ACTIVE_HIGH, gpio_get(GPIO_EC_IN_RW),
+ "EC in RW"},
+ };
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_write_protect_state(void)
+{
+ /* TO_DO:Read PCH_WP GPIO. */
+ return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+ const struct cros_gpio *gpios;
+ size_t num;
+
+ gpios = variant_cros_gpios(&num);
+ chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/shadowmountain/chromeos.fmd b/src/mainboard/intel/shadowmountain/chromeos.fmd
new file mode 100644
index 0000000..4866662
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/chromeos.fmd
@@ -0,0 +1,44 @@
+FLASH@0xfe000000 32M {
+ SI_ALL 0x1081000 {
+ SI_DESC 0x1000
+ SI_EC 0x80000
+ SI_ME
+ }
+ SI_BIOS@0x1400000 0xc00000 {
+ RW_SECTION_A 0x368000 {
+ VBLOCK_A 0x10000
+ FW_MAIN_A(CBFS) 0x357fc0
+ RW_FWID_A 0x40
+ }
+ RW_SECTION_B 0x368000 {
+ VBLOCK_B 0x10000
+ FW_MAIN_B(CBFS) 0x357fc0
+ RW_FWID_B 0x40
+ }
+ RW_MISC 0x30000 {
+ UNIFIED_MRC_CACHE 0x20000 {
+ RECOVERY_MRC_CACHE 0x10000
+ RW_MRC_CACHE 0x10000
+ }
+ RW_ELOG(PRESERVE) 0x4000
+ RW_SHARED 0x4000 {
+ SHARED_DATA 0x2000
+ VBLOCK_DEV 0x2000
+ }
+ RW_VPD(PRESERVE) 0x2000
+ RW_NVRAM(PRESERVE) 0x6000
+ }
+ # RW_LEGACY needs to be minimum of 1MB
+ RW_LEGACY(CBFS) 0x100000
+ WP_RO {
+ RO_VPD(PRESERVE) 0x4000
+ RO_SECTION {
+ FMAP 0x800
+ RO_FRID 0x40
+ RO_FRID_PAD 0x7c0
+ GBB 0x3000
+ COREBOOT(CBFS)
+ }
+ }
+ }
+}
diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl
new file mode 100644
index 0000000..a7e8b62
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/dsdt.asl
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>
+
+DefinitionBlock(
+ "dsdt.aml",
+ "DSDT",
+ ACPI_DSDT_REV_2,
+ OEM_ID,
+ ACPI_TABLE_CREATOR,
+ 0x20110725 // OEM revision
+)
+{
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+ // global NVS and variables
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+ // CPU
+ #include <cpu/intel/common/acpi/cpu.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/tigerlake/acpi/southbridge.asl>
+ #include <soc/intel/tigerlake/acpi/tcss.asl>
+ }
+ }
+
+ // Chrome OS specific
+ #include <vendorcode/google/chromeos/acpi/chromeos.asl>
+
+ // Chrome OS Embedded Controller
+ Scope (\_SB.PCI0.LPCB)
+ {
+ // ACPI code for EC SuperIO functions
+ #include <ec/google/chromeec/acpi/superio.asl>
+ // ACPI code for EC functions
+ #include <ec/google/chromeec/acpi/ec.asl>
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
+
+}
diff --git a/src/mainboard/intel/shadowmountain/ec.c b/src/mainboard/intel/shadowmountain/ec.c
new file mode 100644
index 0000000..e9dc63b
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/ec.c
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <baseboard/ec.h>
+
+void mainboard_ec_init(void)
+{
+ static const struct google_chromeec_event_info info = {
+ .log_events = MAINBOARD_EC_LOG_EVENTS,
+ .sci_events = MAINBOARD_EC_SCI_EVENTS,
+ .s3_wake_events = MAINBOARD_EC_S3_WAKE_EVENTS,
+ .s5_wake_events = MAINBOARD_EC_S5_WAKE_EVENTS,
+ .s0ix_wake_events = MAINBOARD_EC_S0IX_WAKE_EVENTS,
+ };
+
+ google_chromeec_events_init(&info, acpi_is_wakeup_s3());
+}
diff --git a/src/mainboard/intel/shadowmountain/mainboard.c b/src/mainboard/intel/shadowmountain/mainboard.c
new file mode 100644
index 0000000..bb1b412
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/mainboard.c
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <ec/ec.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+#include <smbios.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "board_id.h"
+
+static void mainboard_init(void *chip_info)
+{
+ const struct pad_config *base_pads;
+ const struct pad_config *override_pads;
+ size_t base_num, override_num;
+
+ base_pads = variant_base_gpio_table(&base_num);
+ override_pads = variant_override_gpio_table(&override_num);
+
+ gpio_configure_pads_with_override(base_pads, base_num, override_pads, override_num);
+
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ mainboard_ec_init();
+}
+
+static void mainboard_enable(struct device *dev)
+{
+ dev->ops->acpi_inject_dsdt = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+ .init = mainboard_init,
+ .enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c
new file mode 100644
index 0000000..eb85c55
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/romstage.c
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#include <assert.h>
+#include <console/console.h>
+#include <fsp/api.h>
+#include <soc/romstage.h>
+#include <spd_bin.h>
+#include <string.h>
+#include <soc/meminit.h>
+#include <baseboard/variants.h>
+#include <cbfs.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+ const struct mb_cfg *mem_config = variant_memory_params();
+ const bool half_populated = false;
+//TODO: Need to get the from variant_memory_sku()
+ const struct spd_info lp4_lp5_spd_info = {
+ .read_type = READ_SPD_CBFS,
+ .spd_spec.spd_index = 0,
+ };
+
+ memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
+}
diff --git a/src/mainboard/intel/shadowmountain/smihandler.c b/src/mainboard/intel/shadowmountain/smihandler.c
new file mode 100644
index 0000000..a3b4323
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/smihandler.c
@@ -0,0 +1,30 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <cpu/x86/smm.h>
+#include <ec/google/chromeec/smm.h>
+#include <intelblocks/smihandler.h>
+#include <baseboard/ec.h>
+
+void mainboard_smi_espi_handler(void)
+{
+ if (!CONFIG(EC_GOOGLE_CHROMEEC))
+ return;
+
+ chromeec_smi_process_events();
+}
+
+void mainboard_smi_sleep(u8 slp_typ)
+{
+ if (!CONFIG(EC_GOOGLE_CHROMEEC))
+ return;
+
+ chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
+}
+
+int mainboard_smi_apmc(u8 apmc)
+{
+ if (CONFIG(EC_GOOGLE_CHROMEEC))
+ chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
+
+ return 0;
+}
diff --git a/src/mainboard/intel/shadowmountain/spd/Makefile.inc b/src/mainboard/intel/shadowmountain/spd/Makefile.inc
new file mode 100644
index 0000000..4d79e6d
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/spd/Makefile.inc
@@ -0,0 +1,4 @@
+## SPDX-License-Identifier: GPL-2.0-only
+
+SPD_SOURCES = adlrvp_lp5 # 0b000
+#SPD_SOURCES += empty # 0b001
diff --git a/src/mainboard/intel/shadowmountain/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/shadowmountain/spd/adlrvp_lp5.spd.hex
new file mode 100644
index 0000000..2f2a31a
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/spd/adlrvp_lp5.spd.hex
@@ -0,0 +1,32 @@
+23 10 13 0E 15 1A 95 08 00 40 00 00 02 01 00 00
+48 00 0A FF 92 55 05 00 AA 00 98 A8 90 90 06 C0
+03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 7F 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 20 00 00 00 20 20 20 20 20 20 20
+20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/shadowmountain/spd/empty.spd.hex b/src/mainboard/intel/shadowmountain/spd/empty.spd.hex
new file mode 100644
index 0000000..67b46cd
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
new file mode 100644
index 0000000..4dd8eb6
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/Makefile.inc
@@ -0,0 +1,10 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+##
+
+bootblock-y += gpio.c
+
+romstage-y += memory.c
+
+ramstage-y += gpio.c
+
+smm-y += gpio.c
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
new file mode 100644
index 0000000..daccd3d
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/devicetree.cb
@@ -0,0 +1,278 @@
+chip soc/intel/alderlake
+
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ register "pmc_gpe0_dw0" = "GPP_C"
+ register "pmc_gpe0_dw1" = "GPP_D"
+ register "pmc_gpe0_dw2" = "GPP_E"
+
+ # Enable heci communication
+ register "HeciEnabled" = "1"
+
+ # FSP configuration
+ register "SaGv" = "SaGv_Disabled"
+
+ register "usb2_ports[0]" = "USB2_PORT_MID(OC1)" # Type-A Port A0
+ register "usb2_ports[1]" = "USB2_PORT_MID(OC2)" # Type-A Port A1
+ register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # M.2 WWAN
+ register "usb2_ports[3]" = "USB2_PORT_MID(OC0)" # Type-A / Type-C Cl
+ register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Camera
+ register "usb2_ports[5]" = "USB2_PORT_MID(OC3)" # Type-A / Type-C Co
+ register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth
+
+ register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC1)" # USB3/2 Type A port A0
+ register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB3/2 Type A port A1
+ register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # M.2 WWAN
+
+ # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
+ register "gen1_dec" = "0x00fc0801"
+ register "gen2_dec" = "0x000c0201"
+ # EC memory map range is 0x900-0x9ff
+ register "gen3_dec" = "0x00fc0901"
+
+ register "PrmrrSize" = "0"
+
+ # Enable PCH PCIE RP 5 using CLK 1
+ register "PcieRpEnable[4]" = "1"
+ register "PcieClkSrcClkReq[1]" = "1"
+ register "PcieClkSrcUsage[1]" = "0x4"
+ register "PcieRpClkReqDetect[4]" = "1"
+
+ # Enable PCH PCIE RP 6 using CLK 2
+ register "PcieRpEnable[5]" = "1"
+ register "PcieClkSrcClkReq[2]" = "2"
+ register "PcieClkSrcUsage[2]" = "0x5"
+ register "PcieRpClkReqDetect[5]" = "1"
+
+ # Enable NVMe PCIE 9 using clk 0
+ register "PcieRpEnable[8]" = "1"
+ register "PcieRpLtrEnable[8]" = "1"
+ register "PcieClkSrcUsage[0]" = "8"
+ register "PcieClkSrcClkReq[0]" = "0"
+
+ # Enable SD Card PCIE 8 using clk 3
+ register "PcieRpEnable[7]" = "1"
+ register "PcieRpLtrEnable[7]" = "1"
+ register "PcieRpHotPlug[7]" = "1"
+ register "PcieClkSrcUsage[3]" = "7"
+ register "PcieClkSrcClkReq[3]" = "3"
+
+ # Enable SATA
+ register "SataEnable" = "1"
+ register "SataMode" = "0"
+ register "SataSalpSupport" = "1"
+ register "SataPortsEnable[0]" = "0"
+ register "SataPortsEnable[1]" = "1"
+ register "SataPortsDevSlp[0]" = "0"
+ register "SataPortsDevSlp[1]" = "1"
+ register "SataPortsEnableDitoConfig[1]" = "1"
+
+ register "SerialIoI2cMode" = "{
+ [PchSerialIoIndexI2C0] = PchSerialIoPci,
+ [PchSerialIoIndexI2C1] = PchSerialIoPci,
+ [PchSerialIoIndexI2C2] = PchSerialIoPci,
+ [PchSerialIoIndexI2C3] = PchSerialIoPci,
+ [PchSerialIoIndexI2C4] = PchSerialIoDisabled,
+ [PchSerialIoIndexI2C5] = PchSerialIoPci,
+ }"
+
+ register "SerialIoGSpiMode" = "{
+ [PchSerialIoIndexGSPI0] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI1] = PchSerialIoPci,
+ [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
+ [PchSerialIoIndexGSPI3] = PchSerialIoDisabled,
+ }"
+
+ register "SerialIoGSpiCsMode" = "{
+ [PchSerialIoIndexGSPI0] = 1,
+ [PchSerialIoIndexGSPI1] = 1,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoGSpiCsState" = "{
+ [PchSerialIoIndexGSPI0] = 1,
+ [PchSerialIoIndexGSPI1] = 1,
+ [PchSerialIoIndexGSPI2] = 0,
+ [PchSerialIoIndexGSPI3] = 0,
+ }"
+
+ register "SerialIoUartMode" = "{
+ [PchSerialIoIndexUART0] = PchSerialIoPci,
+ [PchSerialIoIndexUART1] = PchSerialIoDisabled,
+ [PchSerialIoIndexUART2] = PchSerialIoDisabled,
+ }"
+
+ # HD Audio
+ register "PchHdaDspEnable" = "1"
+ register "PchHdaAudioLinkHdaEnable" = "0"
+ register "PchHdaAudioLinkDmicEnable[0]" = "0"
+ register "PchHdaAudioLinkDmicEnable[1]" = "0"
+ register "PchHdaAudioLinkSspEnable[0]" = "0"
+ register "PchHdaAudioLinkSspEnable[1]" = "0"
+ register "PchHdaAudioLinkSndwEnable[0]" = "0"
+ register "PchHdaAudioLinkSndwEnable[1]" = "0"
+
+ # DP port
+ register "DdiPortAConfig" = "1" # eDP
+ register "DdiPortBConfig" = "0"
+
+ register "DdiPortAHpd" = "1"
+ register "DdiPortBHpd" = "1"
+ register "DdiPortCHpd" = "0"
+ register "DdiPort1Hpd" = "1"
+ register "DdiPort2Hpd" = "1"
+ register "DdiPort3Hpd" = "0"
+ register "DdiPort4Hpd" = "0"
+
+ register "DdiPortADdc" = "0"
+ register "DdiPortBDdc" = "1"
+ register "DdiPortCDdc" = "0"
+ register "DdiPort1Ddc" = "0"
+ register "DdiPort2Ddc" = "0"
+ register "DdiPort3Ddc" = "0"
+ register "DdiPort4Ddc" = "0"
+
+ # Intel Common SoC Config
+ #+-------------------+---------------------------+
+ #| Field | Value |
+ #+-------------------+---------------------------+
+ #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT |
+ #| GSPI0 | cr50 TPM. Early init is |
+ #| | required to set up a BAR |
+ #| | for TPM communication |
+ #| | before memory is up |
+ #| GSPI1 | Fingerprint MCU |
+ #| I2C0 | Audio |
+ #| I2C1 | Touchscreen |
+ #| I2C2 | WLAN, SAR0 |
+ #| I2C3 | Camera, SAR1 |
+ #| I2C5 | Trackpad |
+ #+-------------------+---------------------------+
+ register "common_soc_config" = "{
+ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT,
+ .gspi[0] = {
+ .speed_mhz = 1,
+ .early_init = 1,
+ },
+ .i2c[0] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[1] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[2] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[3] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ .i2c[5] = {
+ .speed = I2C_SPEED_FAST,
+ },
+ }"
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Graphics
+ device pci 04.0 on end # DPTF
+ device pci 05.0 on end # IPU
+ device pci 06.0 on end # PEG60
+ device pci 07.0 on end # TBT_PCIe0
+ device pci 07.1 on end # TBT_PCIe1
+ device pci 07.2 on end # TBT_PCIe2
+ device pci 07.3 on end # TBT_PCIe3
+ device pci 08.0 off end # GNA
+ device pci 09.0 off end # NPK
+ device pci 0a.0 off end # Crash-log SRAM
+ device pci 0d.0 on end # USB xHCI
+ device pci 0d.1 on end # USB xDCI (OTG)
+ device pci 0d.2 on end # TBT DMA0
+ device pci 0d.3 on end # TBT DMA1
+ device pci 0e.0 off end # VMD
+ device pci 10.0 off end
+ device pci 10.1 off end
+ device pci 10.2 on end # CNVi: BT
+ device pci 10.6 off end # THC0
+ device pci 10.7 off end # THC1
+ device pci 11.0 off end
+ device pci 11.1 off end
+ device pci 11.2 off end
+ device pci 11.3 off end
+ device pci 11.4 off end
+ device pci 11.5 off end
+ device pci 12.0 off end # SensorHUB
+ device pci 12.5 off end
+ device pci 12.6 off end # GSPI2
+ device pci 13.0 off end # GSPI3
+ device pci 13.1 off end
+ device pci 14.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Root Hub""
+ register "type" = "UPC_TYPE_HUB"
+ device usb 0.0 on
+ chip drivers/usb/acpi
+ register "desc" = ""Bluetooth""
+ register "type" = "UPC_TYPE_INTERNAL"
+ device usb 2.9 on end
+ end
+ end
+ end
+ end # USB3.1 xHCI
+ device pci 14.1 off end # USB3.1 xDCI
+ device pci 14.2 off end # Shared RAM
+ device pci 14.3 on
+ chip drivers/wifi/generic
+ register "wake" = "GPE0_PME_B0"
+ device generic 0 on end
+ end
+ end # CNVi: WiFi
+ device pci 15.0 on end # I2C0
+ device pci 15.1 on end # I2C1
+ device pci 15.2 on end # I2C2
+ device pci 15.3 on end # I2C3
+ device pci 16.0 off end # HECI1
+ device pci 16.1 off end # HECI2
+ device pci 16.2 off end # CSME
+ device pci 16.3 off end # CSME
+ device pci 16.4 off end # HECI3
+ device pci 16.5 off end # HECI4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C4
+ device pci 19.1 on end # I2C5
+ device pci 19.2 off end # UART2
+ device pci 1c.0 on end # RP1
+ device pci 1c.1 off end # RP2
+ device pci 1c.2 off end # RP3
+ device pci 1c.3 off end # RP4
+ device pci 1c.4 on end # RP5
+ device pci 1c.5 on end # RP6
+ device pci 1c.6 off end # RP7
+ device pci 1c.7 off end # RP8
+ device pci 1d.0 on end # RP9
+ device pci 1d.1 off end # RP10
+ device pci 1d.2 on end # RP11
+ device pci 1d.3 off end # RP12
+ device pci 1e.0 on end # UART0
+ device pci 1e.1 off end # UART1
+ device pci 1e.2 on end # GSPI0
+ device pci 1e.3 off end # GSPI1
+ device pci 1f.0 on
+ chip ec/google/chromeec
+ device pnp 0c09.0 on end
+ end
+ end # eSPI
+ device pci 1f.1 on end # P2SB
+ device pci 1f.2 hidden end # PMC
+ device pci 1f.3 on end # Intel Audio SNDW
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
new file mode 100644
index 0000000..e63416c
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/gpio.c
@@ -0,0 +1,418 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage */
+/* Leave eSPI pins untouched from default settings */
+static const struct pad_config gpio_table[] = {
+ /* A0-A4 A9-A10 come configured out of reset, do not touch */
+ /* A0 : ESPI_IO0 ==> ESPI_IO_0 */
+ /* A1 : ESPI_IO1 ==> ESPI_IO_1 */
+ /* A2 : ESPI_IO2 ==> ESPI_IO_2 */
+ /* A3 : ESPI_IO3 ==> ESPI_IO_3 */
+ /* A4 : ESPI_CS# ==> ESPI_CS_L */
+ /* A9 : ESPI_CLK ==> ESPI_CLK */
+ /* A10 : ESPI_RESET# ==> NC(TP764) */
+ /* A5 : USB_C0_AUXP_DC */
+ PAD_NC(GPP_A5, NONE),
+ /* A6 : USB_C0_AUXN_DC */
+ PAD_NC(GPP_A6, NONE),
+ /* A8 : EC_IN_RW_OD */
+ PAD_CFG_GPI(GPP_A8, NONE, DEEP),
+ /* A11 : PMC_I2C_SDA ==> SSD_PERST_L */
+ PAD_CFG_GPO(GPP_A11, 1, DEEP),
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+ /* A13 : BT_DISABLE_L */
+ PAD_CFG_GPO(GPP_A13, 1, DEEP),
+ /* A14 : USB_OC1# ==> USB_A0_OC_ODL */
+ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
+ /* A15 : USB_OC2# ==> USB_A1_OC_ODL */
+ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
+ /* A16 : USB_C0_OC_ODL */
+ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
+ /* A18 : HDMI_HPD */
+ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
+ /* A21 : EN_FP_PWR */
+ PAD_CFG_GPO(GPP_A21, 1, DEEP),
+ /* A22 : EN_HDMI_PWR */
+ PAD_CFG_GPO(GPP_A22, 1, DEEP),
+ /* A23 : EN_SPKR_PA */
+ PAD_CFG_GPO(GPP_A23, 1, DEEP),
+
+ /* B0 : CORE_VID0 */
+ PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
+ /* B1 : CORE_VID1 */
+ PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
+ /* B2 : VRALERT# ==> VRALERT_L */
+ PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1),
+ /* B3 : PEN_DET_ODL */
+ PAD_NC(GPP_B3, NONE),
+ /* B4 : WiFi_DISABLE_L */
+ PAD_CFG_GPO(GPP_B4, 1, DEEP),
+ /* B5 : PCH_I2C2_1V8_AUDIO_SDA */
+ PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2),
+ /* B6 : PCH_I2C2_1V8_AUDIO_SCL */
+ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2),
+ /* B7 : PCH_I2C3_TOUCH_USI_SDA */
+ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
+ /* B8 : PCH_I2C3_TOUCH_USI_SCL */
+ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
+ /* B9 : I2C5_SDA ==> NC */
+ PAD_NC(GPP_B9, NONE),
+ /* B10 : I2C5_SCL ==> NC */
+ PAD_NC(GPP_B10, NONE),
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+ /* B12 : SLP_S0# ==> SLP_S0_L */
+ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
+ /* B13 : PLTRST# ==> PLT_RST_L */
+ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
+ /* B14 : SPKR ==> GPP_B14_STRAP */
+ PAD_NC(GPP_B14, NONE),
+ /* B15 : FPMCU_INT_L */
+ PAD_NC(GPP_B15, NONE),
+ /* B16 : PCH_I2C5_TRACKPAD_SDA */
+ PAD_CFG_NF(GPP_B16, NONE, DEEP, NF2),
+ /* B17 : PCH_I2C5_TRACKPAD_SCL */
+ PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
+ /* B18 : EN_PP5000_TRACKPAD */
+ PAD_CFG_GPO(GPP_B18, 1, DEEP),
+ /* B19 : NC */
+ PAD_NC(GPP_B19, NONE),
+ /* B20 : NC */
+ PAD_NC(GPP_B20, NONE),
+ /* B21 : NC */
+ PAD_NC(GPP_B21, NONE),
+ /* B22 : NC */
+ PAD_NC(GPP_B22, NONE),
+ /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */
+ PAD_NC(GPP_B23, NONE),
+
+ /* C0 : EN_PP3300_WLAN */
+ PAD_CFG_GPO(GPP_C0, 1, DEEP),
+ /* C1 : USI_RST_L */
+ PAD_CFG_GPO(GPP_C1, 0, DEEP),
+ /* C2 : SMBALERT# ==> GPP_C2_STRAP */
+ PAD_NC(GPP_C2, NONE),
+ /* C3 : H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+ /* C4 : EN_PP5000_PEN */
+ PAD_CFG_GPO(GPP_C4, 1, DEEP),
+ /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */
+ PAD_NC(GPP_C5, NONE),
+ /* C6 : SML1CLK ==> EC_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C6, NONE, PLTRST, LEVEL, INVERT),
+ /* C7 : FPMCU_RST_ODL */
+ PAD_CFG_GPO(GPP_C7, 1, DEEP),
+
+ /* D0 : SSD_RTD3_EN */
+ PAD_CFG_GPO(GPP_D0, 1, DEEP),
+ /* D1 : ISH_GP1 ==> NC */
+ PAD_NC(GPP_D1, NONE),
+ /* D2 : ISH_GP2 ==> NC */
+ PAD_NC(GPP_D2, NONE),
+ /* D3 : ISH_GP3 ==> NC */
+ PAD_NC(GPP_D3, NONE),
+ /* D4 : FCAM_RST_L */
+ PAD_CFG_GPO(GPP_D4, 0, PLTRST),
+ /* D5 : SSD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
+ /* D6 : WLAN_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
+ /* D8 : SD_CLKREQ_ODL */
+ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
+ /* D9 : SD_PE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_D9, NONE, DEEP),
+ /* D10 : EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+ /* D11 : PEN_ALERT_ODL */
+ PAD_CFG_GPI(GPP_D11, NONE, DEEP),
+ /* D12 : PCH_FPMCU_BOOT0 */
+ PAD_CFG_GPO(GPP_D12, 0, DEEP),
+ /* D13 : UART_ISH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1),
+ /* D14 : UART_ISH_TX_DEBUG_RX */
+ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
+ /* D16 : EN_PP3300_SD */
+ PAD_CFG_GPO(GPP_D16, 1, DEEP),
+ /* D17 : EN_FCAM_PWR */
+ PAD_CFG_GPO(GPP_D17, 1, DEEP),
+ /* D18 : EN_FCAM_SNR_PWR */
+ PAD_CFG_GPO(GPP_D18, 1, DEEP),
+ /* D19 : I2S_MCLK1 ==> I2S_MCLK1 */
+ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
+
+ /* E0 : SATAXPCIE0 ==> USB_A1_RT_RST_ODL */
+ PAD_CFG_GPO(GPP_E0, 1, DEEP),
+ /* E1 : PEN_DET_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_E1, NONE, DEEP, EDGE_SINGLE),
+ /* E2 : WLAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
+ /* E3 : USI_REPORT_EN */
+ PAD_CFG_GPO(GPP_E3, 0, DEEP),
+ /* E4 : SATA_DEVSLP0 ==> M2_SSD_PE_WAKE_ODL */
+ PAD_NC(GPP_E4, NONE),
+ /* E5 : SATA_DEVSLP1 ==> M2_SSD_DEVSLP_OD */
+ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1),
+ /* E6 : THC0_SPI1_RST# ==> GPPE6_STRAP */
+ PAD_NC(GPP_E6, NONE),
+ /* E7 : USI_INT */
+ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
+ /* E8 : SLP_S0IX */
+ PAD_CFG_GPO(GPP_E8, 0, DEEP),
+ /* E9 : USB2_OC0# ==> USB_C1_OC_ODL */
+ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
+ /* E10 : PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
+ /* E11 : PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
+ /* E12 : PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
+ /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
+ /* E14 : DDPC_HPDA ==> SOC_EDP_HPD */
+ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
+ /* E15 : WWAN_CONFIG0 */
+ PAD_CFG_GPI(GPP_E15, NONE, DEEP),
+ /* E16 : FPMCU_INT_L */
+ PAD_CFG_GPI_INT(GPP_E16, NONE, PLTRST, LEVEL),
+ /* E17 : WWAN_PERST_L */
+ PAD_CFG_GPO(GPP_E17, 1, DEEP),
+ /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4),
+ /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4),
+ /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
+ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF4),
+ /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
+ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF4),
+ /* E22 : DDPA_CTRLCLK ==> USB_C1_AUXP_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E22, NONE),
+ /* E23 : DDPA_CTRLDATA ==> USB_C1_AUXN_DC: Retimer FW drives this pin */
+ PAD_NC(GPP_E23, NONE),
+
+ /* F0 : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
+ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
+ /* F1 : CNV_BRI_RSP ==> NCV_BRI_RSP */
+ PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1),
+ /* F2 : I2S2_TXD ==> CNV_RGI_DT_STRAP */
+ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1),
+ /* F3 : I2S2_RXD ==> CNV_RGI_RSP */
+ PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1),
+ /* F4 : CNV_RF_RESET# ==> CNV_RF_RST_L */
+ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
+ /* F5 : MODEM_CLKREQ ==> CNV_CLKREQ0 */
+ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2),
+ /* F6 : WWAN_CONFIG3 */
+ PAD_CFG_GPI(GPP_F6, NONE, DEEP),
+ /* A7 : EN_PP3300_TRACKPAD */
+ PAD_CFG_GPO(GPP_F7, 1, DEEP),
+ /* F8 : I2S_MCLK2_INOUT ==> NC */
+ PAD_NC(GPP_F8, NONE),
+ /* F9 : HP_INT_L */
+ PAD_CFG_GPI_INT(GPP_F9, NONE, PLTRST, EDGE_BOTH),
+ /* F10 : EN_PP3300_TOUCHSCREEN */
+ PAD_CFG_GPO(GPP_F10, 0, DEEP),
+ /* F11 : PCH_GSPI1_FPMCU_CLK */
+ PAD_CFG_NF(GPP_F11, NONE, DEEP, NF4),
+ /* F12 : PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF4),
+ /* F13 : PCH_GSPI1_FPMCU_MISO */
+ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF4),
+ /* F14 : WLAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F14, 1, DEEP),
+ /* F15 : RCAM_RST_L */
+ PAD_CFG_GPO(GPP_F15, 1, DEEP),
+ /* F16 : PCH_GSPI1_FPMCU_CS_L */
+ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF4),
+ /* F17 : WWAN_RF_DISABLE_ODL */
+ PAD_CFG_GPO(GPP_F17, 1, DEEP),
+ /* F18 : WWAN_PCIE_WAKE_ODL */
+ PAD_CFG_GPI_SCI_LOW(GPP_F18, NONE, DEEP, EDGE_SINGLE),
+ /* F19 : WLAN_INT_L */
+ PAD_CFG_GPI_SCI_LOW(GPP_F19, NONE, DEEP, EDGE_SINGLE),
+ /* F20 : WWAN_RST_ODL */
+ PAD_CFG_GPO(GPP_F20, 1, DEEP),
+ /* F21 : WWAN_DPR_SAR_ODL */
+ PAD_CFG_GPO(GPP_F21, 1, DEEP),
+ /* F22 : VNN_CTRL */
+ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
+ /* F23 : V1P05_CTRL */
+ PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
+
+ /* H0 : GPPH0_BOOT_STRAP1 */
+ PAD_NC(GPP_H0, NONE),
+ /* H1 : GPPH1_BOOT_STRAP2 */
+ PAD_NC(GPP_H1, NONE),
+ /* H2 : GPPH2_BOOT_STRAP3 */
+ PAD_NC(GPP_H2, NONE),
+ /* H3 : SD_PERST_L */
+ PAD_CFG_GPO(GPP_H3, 1, DEEP),
+ /* H4 : PCH_I2C0_MISC_SDA */
+ PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
+ /* H5 : PCH_I2C0_MISC_SCL */
+ PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
+ /* H6 : I2C3_SDA ==> PCH_I2C3_MISC_SDA */
+ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
+ /* H7 : I2C3_SCL ==> PCH_I2C3_MISC_SCL */
+ PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
+ /* H8 : WWAN_WLAN_COEX1 */
+ PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2),
+ /* H9 : WWAN_WLAN_COEX2 */
+ PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2),
+ /* H10 : UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
+ /* H11 : UART_PCH_RX_DEBUG_TX */
+ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
+/* H12 : WWAN_CONFIG0 */
+ PAD_NC(GPP_H12, NONE),
+/* H13 : EN_RCAM_SNR_PWR */
+ PAD_NC(GPP_H13, NONE),
+ /* H14 : M2_SKT2_CFG2 # ==> NC */
+ PAD_NC(GPP_H14, NONE),
+ /* H15 : DDPB_HDMI_CTRLCLK */
+ PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1),
+ /* H17 : DDPB_HDMI_CTRLDATA */
+ PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
+ /* H18 : CPU_C10_GATE# ==> CPU_C10_GATE_L */
+ PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
+/* H19 : USB_C1_RT_FORCE_PWR */
+ PAD_NC(GPP_H19, NONE),
+ /* H20 : EN_MIPI_RCAM_PWR */
+ PAD_CFG_GPO(GPP_H20, 0, DEEP),
+ /* H21 : CAM_MCLK1 */
+ PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+ /* H22 : CAM_MCLK0 */
+ PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+/* H23 : WWAN_ESIM_SEL_ODL */
+ PAD_NC(GPP_H23, NONE),
+
+ /* R0 : I2S0_HP_SCLK */
+ PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
+ /* R1 : I2S0_HP_SFRM */
+ PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
+ /* R2 : I2S0_PCH_TX_HP_RX_STRAP */
+ PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2),
+ /* R3 : I2S0_PCH_RX_HP_TX */
+ PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
+ /* R4 : DMIC_CLK0 */
+ PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
+ /* R5 : DMIC_DATA0 */
+ PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
+/* R6 : WWAN_WLAN_COEX3 */
+ PAD_NC(GPP_R6, NONE),
+/* R7 : SAR0_INT_L */
+ PAD_NC(GPP_R7, NONE),
+
+/* S0 : SNDW0_CLK ==> NC */
+ PAD_NC(GPP_S0, NONE),
+ /* S1 : SNDW0_DATA ==> NC */
+ PAD_NC(GPP_S1, NONE),
+ /* S2 : SNDW1_CLK ==> NC */
+ PAD_NC(GPP_S2, NONE),
+ /* S3 : SNDW1_DATA ==> NC */
+ PAD_NC(GPP_S3, NONE),
+ /* S4 : SNDW2_CLK ==> NC */
+ PAD_NC(GPP_S4, NONE),
+ /* S5 : SNDW2_DATA ==> NC */
+ PAD_NC(GPP_S5, NONE),
+ /* S6 : SNDW3_CLK ==> NC */
+ PAD_NC(GPP_S6, NONE),
+ /* S7 : SNDW3_DATA ==> NC */
+ PAD_NC(GPP_S7, NONE),
+
+ /* GPD0: BATLOW# ==> BATLOW_L */
+ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
+ /* GPD1: ACPRESENT ==> PCH_ACPRESENT */
+ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
+ /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
+ PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
+ /* GPD3: PWRBTN# ==> EC_PCH_PWR_BTN_ODL */
+ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
+ /* GPD4: SLP_S3# ==> SLP_S3_L */
+ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
+ /* GPD5: SLP_S4# ==> SLP_S4_L */
+ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
+ /* GPD6: SLP_A# ==> SLP_A_L */
+ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
+ /* GPD7: GPD7_STRAP */
+ PAD_CFG_GPI(GPD7, DN_20K, DEEP),
+ /* GPD8: SUSCLK ==> PCH_SUSCLK */
+ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
+ /* GPD9: SLP_WLAN# ==> NC */
+ PAD_NC(GPD9, NONE),
+ /* GPD10: SLP_S5# ==> SLP_S5_L */
+ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
+ /* GPD11: LANPHYC ==> NC */
+ PAD_CFG_NF(GPD11, NONE, DEEP, NF1),
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+
+ /* A7 : MEM_STRAP_0 */
+ PAD_CFG_GPI(GPP_A7, NONE, DEEP),
+ /* A17 : MEM_CH_SEL */
+ PAD_CFG_GPI(GPP_A17, NONE, DEEP),
+ /* A19 : MEM_STRAP_2 */
+ PAD_CFG_GPI(GPP_A19, NONE, DEEP),
+ /* A20 : MEM_STRAP_1 */
+ PAD_CFG_GPI(GPP_A20, NONE, DEEP),
+ /* D15 : MEM_STRAP_3 */
+ PAD_CFG_GPI(GPP_D15, NONE, DEEP),
+
+ /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */
+ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1),
+
+ /* B11 : PMCALERT# ==> PCH_WP_OD */
+ PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP),
+
+ /* E10 : PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF7),
+ /* E11 : PCH_GSPI0_H1_TPM_CLK */
+ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF7),
+ /* E12 : PCH_GSPIO_H1_TPM_MISO */
+ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF7),
+ /* E13 : PCH_GSPI0_H1_TPM_MOSI_STRAP */
+ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF7),
+ /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */
+ PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
+
+ /* C3 : H1_PCH_INT_ODL */
+ PAD_CFG_GPI_APIC(GPP_C3, NONE, PLTRST, LEVEL, INVERT),
+
+ /* D10 : EN_PP3300_WWAN */
+ PAD_CFG_GPO(GPP_D10, 1, DEEP),
+};
+
+const struct pad_config *__weak variant_base_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(gpio_table);
+ return gpio_table;
+}
+
+const struct pad_config *__weak variant_override_gpio_table(size_t *num)
+{
+ *num = 0;
+ return NULL;
+}
+
+const struct pad_config *__weak variant_early_gpio_table(size_t *num)
+{
+ *num = ARRAY_SIZE(early_gpio_table);
+ return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+ CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+ CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *__weak variant_cros_gpios(size_t *num)
+{
+ *num = ARRAY_SIZE(cros_gpios);
+ return cros_gpios;
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000..7dc9572
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,76 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __MAINBOARD_EC_H__
+#define __MAINBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_USB_MUX))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/* EC can wake from S3 with lid, power button or mode change event */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+ (MAINBOARD_EC_S5_WAKE_EVENTS |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+#define MAINBOARD_EC_S0IX_WAKE_EVENTS (MAINBOARD_EC_S3_WAKE_EVENTS)
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+ (EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+ EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN GPE_EC_WAKE
+
+/* Enable Tablet switch */
+#define EC_ENABLE_TBMC_DEVICE
+
+#define SIO_EC_MEMMAP_ENABLE /* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */
+
+/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in variant/gpio.h */
+#define EC_ENABLE_SYNC_IRQ
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable EC backed Keyboard Backlight in ACPI */
+#define EC_ENABLE_KEYBOARD_BACKLIGHT
+
+#endif /* __MAINBOARD_EC_H__ */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000..3776dba
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* EC in RW */
+#define GPIO_EC_IN_RW GPP_A8
+
+/* BIOS Flash Write Protect */
+#define GPIO_PCH_WP GPP_B11
+
+/* EC wake is LAN_WAKE# */
+#define GPE_EC_WAKE GPE0_LAN_WAK
+
+/* EC sync IRQ */
+#define EC_SYNC_IRQ GPP_C6_IRQ
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI GPE0_ESPI
+
+/* DRAM population strap (value 0=fully-populated, 1=half-populated) */
+#define GPIO_MEM_CH_SEL GPP_A17
+
+#endif /* BASEBOARD_GPIO_H */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000..7137d56
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <soc/meminit.h>
+#include <stddef.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/*
+ * The next set of functions return the gpio table and fill in the number of
+ * entries for each table.
+ */
+const struct pad_config *variant_base_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct pad_config *variant_override_gpio_table(size_t *num);
+
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+const struct mb_cfg *variant_memory_params(void);
+int variant_memory_sku(void);
+
+#endif /* __BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c b/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c
new file mode 100644
index 0000000..dcb472a
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/baseboard/memory.c
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <baseboard/variants.h>
+#include <gpio.h>
+#include <soc/romstage.h>
+
+static const struct mb_cfg lp5_mem_config = {
+ /* DQ CPU<>DRAM map */
+ .dq_map = {
+ { 10, 8, 9, 12, 15, 13, 14, 11, /* DDR0_DQ0[7:0] */
+ 2, 6, 3, 7, 5, 1, 4, 0 }, /* DDR0_DQ1[7:0] */
+ { 2, 0, 3, 1, 6, 4, 7, 5, /* DDR1_DQ0[7:0] */
+ 8, 9, 10, 11, 13, 12, 14, 15 }, /* DDR1_DQ1[7:0] */
+ { 1, 0, 3, 2, 6, 4, 5, 7, /* DDR2_DQ0[7:0] */
+ 12, 13, 8, 9, 15, 11, 14, 10 }, /* DDR2_DQ1[7:0] */
+ { 8, 9, 11, 10, 13, 15, 14, 12, /* DDR3_DQ0[7:0] */
+ 6, 5, 4, 7, 3, 2, 0, 1 }, /* DDR3_DQ1[7:0] */
+ { 8, 13, 9, 12, 15, 11, 14, 10, /* DDR4_DQ0[7:0] */
+ 2, 7, 3, 6, 5, 1, 4, 0 }, /* DDR4_DQ1[7:0] */
+ { 0, 2, 1, 3, 6, 7, 4, 5, /* DDR5_DQ0[7:0] */
+ 13, 12, 15, 14, 10, 9, 8, 11 }, /* DDR5_DQ1[7:0] */
+ { 8, 13, 9, 12, 15, 10, 14, 11, /* DDR6_DQ0[7:0] */
+ 3, 6, 2, 7, 4, 1, 0, 5 }, /* DDR6_DQ1[7:0] */
+ { 11, 9, 10, 8, 12, 14, 13, 15, /* DDR7_DQ0[7:0] */
+ 4, 6, 1, 0, 7, 3, 2, 5 } /* DDR7_DQ1[7:0] */
+ },
+
+ /* DQS CPU<>DRAM map */
+ .dqs_map = {
+ { 1, 0 }, /* DDR0_DQS[1:0] */
+ { 0, 1 }, /* DDR1_DQS[1:0] */
+ { 0, 1 }, /* DDR2_DQS[1:0] */
+ { 1, 0 }, /* DDR3_DQS[1:0] */
+ { 1, 0 }, /* DDR4_DQS[1:0] */
+ { 0, 1 }, /* DDR5_DQS[1:0] */
+ { 1, 0 }, /* DDR6_DQS[1:0] */
+ { 1, 0 } /* DDR7_DQS[1:0] */
+ },
+
+ .dq_pins_interleaved = false,
+
+ .ect = false, /* Early Command Training */
+
+ .lp5_ccc_config = 0xD0,
+
+ .UserBd = BOARD_TYPE_MOBILE,
+};
+
+const struct mb_cfg *variant_memory_params(void)
+{
+ return &lp5_mem_config;
+}
+
+int variant_memory_sku(void)
+{
+ gpio_t spd_gpios[] = {
+ GPP_A7,
+ GPP_A20,
+ GPP_A19,
+ GPP_D15,
+ };
+
+ return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
+}
diff --git a/src/mainboard/intel/shadowmountain/variants/shadowmountain/overridetree.cb b/src/mainboard/intel/shadowmountain/variants/shadowmountain/overridetree.cb
new file mode 100644
index 0000000..f1cc1e7
--- /dev/null
+++ b/src/mainboard/intel/shadowmountain/variants/shadowmountain/overridetree.cb
@@ -0,0 +1,5 @@
+chip soc/intel/alderlake
+
+ device domain 0 on end
+end
+
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