Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu.
Shuo Liu has uploaded this change for review.
soc/intel/xeon_sp: Support CHIPSET_LOCKDOWN_FSP
In a server platform many silicon specific register lock operations
are by default in FSP space. CHIPSET_LOCKDOWN_FSP provides an option
to make sure the codes could be used out-of-box to build products.
Change-Id: I8efcc1f27446be8e35f51e2568c4af6f8165486b
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
---
M src/soc/intel/xeon_sp/lockdown.c
1 file changed, 4 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/82081/1
diff --git a/src/soc/intel/xeon_sp/lockdown.c b/src/soc/intel/xeon_sp/lockdown.c
index 9e25920..a3d17b4 100644
--- a/src/soc/intel/xeon_sp/lockdown.c
+++ b/src/soc/intel/xeon_sp/lockdown.c
@@ -1,5 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
+#include <intelblocks/cfg.h>
#include <intelblocks/lpc_lib.h>
#include <intelpch/lockdown.h>
#include <soc/lockdown.h>
@@ -20,6 +21,9 @@
void soc_lockdown_config(int chipset_lockdown)
{
+ if (chipset_lockdown == CHIPSET_LOCKDOWN_FSP)
+ return;
+
lpc_lockdown_config();
pmc_lockdown_config();
sata_lockdown_config(chipset_lockdown);
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