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4 comments:
File src/mainboard/google/dedede/Kconfig:
Patch Set #5, Line 16: select GENERIC_SPD_BIN
Nit: Sorted in alphabetical order. Move it after select EC_GOOGLE_CHROMEEC_SPI
Patch Set #5, Line 72: config DIMM_SPD_SIZE
Nit: Move it after config DEVICETREE. This is sorted in alphabetical order.
File src/mainboard/google/dedede/romstage.c:
* Copyright (C) 2020 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
Not sure if it is the appropriate license header. I thought we are adopting "The coreboot project Authors" and SPDX License Identifier.
File src/mainboard/google/dedede/variants/waddledoo/memory.c:
Patch Set #5, Line 23: SMBUS
CBFS
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