1 comment:
File src/soc/intel/alderlake/romstage/fsp_params.c:
Patch Set #9, Line 40: config->PcieRp[i].clkreq
I think you thought is PCIE port in schematic is 1-10 and CLKREQ/CLKSRC is 0-9. […]
Yes, I think it would be better to keep the root port # such that is matches the schematic. You can use 1-X for root port numbers and let 0 be unused or use enums for that as well:
enum pcie_rp {
RP_1 = 0,
RP_2,
RP_3,
...
}
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