Meera Ravindranath has uploaded this change for review.
mb/intel/adlrvp: Add support for DDR5 MR SKU
DDR5 Maple ridge SKU uses a Memory down DIMM configuration.
This CL adds support for the same.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I0b7a96b5534d8b80776aa7578ce7c13181af7882
---
M src/mainboard/intel/adlrvp/romstage_fsp_params.c
M src/mainboard/intel/adlrvp/spd/Makefile.inc
A src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
3 files changed, 41 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/56881/1
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index cccd258..df08e50 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -35,6 +35,11 @@
.cbfs_index = get_spd_index(),
};
+ const struct mem_spd mr_ddr5_spd_info = {
+ .topo = MEM_TOPO_MEMORY_DOWN,
+ .cbfs_index = get_spd_index(),
+ };
+
const struct mem_spd ddr4_ddr5_spd_info = {
.topo = MEM_TOPO_DIMM_MODULE,
.smbus = {
@@ -53,9 +58,11 @@
case ADL_P_DDR4_1:
case ADL_P_DDR4_2:
case ADL_P_DDR5_1:
- case ADL_P_DDR5_2:
memcfg_init(m_cfg, mem_config, &ddr4_ddr5_spd_info, half_populated);
break;
+ case ADL_P_DDR5_2:
+ memcfg_init(m_cfg, mem_config, &mr_ddr5_spd_info, half_populated);
+ break;
case ADL_P_LP4_1:
case ADL_P_LP4_2:
case ADL_P_LP5_1:
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
index 5c5c1b4..4ab055d 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -6,5 +6,5 @@
SPD_SOURCES += adlrvp_lp5 # 0b003
SPD_SOURCES += empty # 0b004
SPD_SOURCES += empty # 0b005
-SPD_SOURCES += empty # 0b006
+SPD_SOURCES += adlrvp_ddr5_mr # 0b006
SPD_SOURCES += adlrvp_lp5 # 0b007
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
new file mode 100644
index 0000000..80ef521
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_ddr5_mr.spd.hex
@@ -0,0 +1,32 @@
+30 08 12 03 04 00 20 62 00 00 00 00 60 00 00 00
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+1E 41 1E 41 00 7D 1E BE 30 75 27 01 A0 00 82 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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