Arthur Heymans has uploaded this change for review.

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[TESTME]mb/asus/{p5gc-mx,p5qpl-am}: Use system_reset instead of full_reset

The GMCH needs to sample BSEL again after the SuperIO GPIO to
configure BSEL have been set. This happens when RSTIN# is asserted,
which in turn happens when PCIRST# is asserted by the southbridge.

This needs to be tested on hardware.

Change-Id: I246ac15d0d12ffc18686c7d22a9e6c2b43dce535
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/mainboard/asus/p5gc-mx/romstage.c
M src/mainboard/asus/p5qpl-am/romstage.c
2 files changed, 10 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/36312/1

diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 20a2b56..0814203 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -182,7 +182,11 @@
 	if (!s3resume && setup_sio_gpio(c_bsel)) {
 		printk(BIOS_DEBUG,
 			"Needs reset to configure CPU BSEL straps\n");
-		full_reset();
+		/* BSEL is resampled if GMCH RSTIN# is asserted which
+		   in it turn gets asserted by PCIRST#. */
+		pci_update_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0,
+				    PCI_BRIDGE_CTL_BUS_RESET);
+		system_reset();
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 30480ad..c60b4d2 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -184,7 +184,11 @@
 	if (!s3_resume && setup_sio_gpio()) {
 		printk(BIOS_DEBUG,
 		       "Needs reset to configure CPU BSEL straps\n");
-		full_reset();
+		/* BSEL is resampled if GMCH RSTIN# is asserted which
+		   in it turn gets asserted by PCIRST#. */
+		pci_update_config16(PCI_DEV(0, 0x1e, 0), PCI_BRIDGE_CONTROL, 0,
+				    PCI_BRIDGE_CTL_BUS_RESET);
+		system_reset();
 	}
 
 	sdram_initialize(boot_path, spd_addrmap);

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