Elyes HAOUAS has uploaded this change for review.
src: Move IA32_{FEATURE_CONTROL,MCG_CAP} to x86/msr.h
Change-Id: I36a84896187558e16f6a960839c890a89ff2ac09
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
---
M src/cpu/intel/common/common_init.c
M src/cpu/intel/fsp_model_206ax/model_206ax.h
M src/cpu/intel/fsp_model_406dx/model_406dx.h
M src/cpu/intel/haswell/haswell.h
M src/cpu/intel/haswell/haswell_init.c
M src/cpu/intel/model_2065x/model_2065x.h
M src/cpu/intel/model_206ax/model_206ax.h
M src/cpu/intel/smm/gen1/smmrelocate.c
M src/include/cpu/x86/msr.h
M src/soc/intel/baytrail/romstage/cache_as_ram.inc
M src/soc/intel/broadwell/include/soc/msr.h
M src/soc/intel/common/block/include/intelblocks/msr.h
M src/soc/intel/common/block/sgx/sgx.c
M src/soc/intel/common/block/vmx/vmx.c
M src/soc/intel/denverton_ns/include/soc/msr.h
M src/soc/intel/fsp_broadwell_de/include/soc/msr.h
16 files changed, 15 insertions(+), 43 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/28852/1
diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c
index 8dd8559..98b7f58 100644
--- a/src/cpu/intel/common/common_init.c
+++ b/src/cpu/intel/common/common_init.c
@@ -20,7 +20,6 @@
#include <cpu/x86/msr.h>
#include "common.h"
-#define IA32_FEATURE_CONTROL 0x3a
#define CPUID_VMX (1 << 5)
#define CPUID_SMX (1 << 6)
diff --git a/src/cpu/intel/fsp_model_206ax/model_206ax.h b/src/cpu/intel/fsp_model_206ax/model_206ax.h
index e65b370..7db870d 100644
--- a/src/cpu/intel/fsp_model_206ax/model_206ax.h
+++ b/src/cpu/intel/fsp_model_206ax/model_206ax.h
@@ -20,9 +20,6 @@
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
diff --git a/src/cpu/intel/fsp_model_406dx/model_406dx.h b/src/cpu/intel/fsp_model_406dx/model_406dx.h
index 87daeac..953fdca 100644
--- a/src/cpu/intel/fsp_model_406dx/model_406dx.h
+++ b/src/cpu/intel/fsp_model_406dx/model_406dx.h
@@ -21,9 +21,6 @@
/* Rangeley bus clock is fixed at 100MHz */
#define RANGELEY_BCLK 100
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
diff --git a/src/cpu/intel/haswell/haswell.h b/src/cpu/intel/haswell/haswell.h
index 8498c1a..51a0deb 100644
--- a/src/cpu/intel/haswell/haswell.h
+++ b/src/cpu/intel/haswell/haswell.h
@@ -35,9 +35,6 @@
#define HASWELL_BCLK 100
#define CORE_THREAD_COUNT_MSR 0x35
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c
index 24de43e..5ea8535 100644
--- a/src/cpu/intel/haswell/haswell_init.c
+++ b/src/cpu/intel/haswell/haswell_init.c
@@ -661,11 +661,10 @@
static void configure_mca(void)
{
msr_t msr;
- const unsigned int mcg_cap_msr = 0x179;
int i;
int num_banks;
- msr = rdmsr(mcg_cap_msr);
+ msr = rdmsr(IA32_MCG_CAP);
num_banks = msr.lo & 0xff;
msr.lo = msr.hi = 0;
/* TODO(adurbin): This should only be done on a cold boot. Also, some
diff --git a/src/cpu/intel/model_2065x/model_2065x.h b/src/cpu/intel/model_2065x/model_2065x.h
index f87ba77..521e806 100644
--- a/src/cpu/intel/model_2065x/model_2065x.h
+++ b/src/cpu/intel/model_2065x/model_2065x.h
@@ -20,9 +20,6 @@
/* Nehalem bus clock is fixed at 133MHz */
#define NEHALEM_BCLK 133
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
diff --git a/src/cpu/intel/model_206ax/model_206ax.h b/src/cpu/intel/model_206ax/model_206ax.h
index 98203b6..9ab7466 100644
--- a/src/cpu/intel/model_206ax/model_206ax.h
+++ b/src/cpu/intel/model_206ax/model_206ax.h
@@ -20,9 +20,6 @@
/* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
#define SANDYBRIDGE_BCLK 100
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_FEATURE_CONFIG 0x13c
#define MSR_FLEX_RATIO 0x194
#define FLEX_RATIO_LOCK (1 << 20)
@@ -39,7 +36,6 @@
#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2
#define MSR_LT_LOCK_MEMORY 0x2e7
#define IA32_MC0_STATUS 0x401
-#define IA32_MCG_CAP 0x179
#define MSR_PIC_MSG_CONTROL 0x2e
#define MSR_PLATFORM_INFO 0xce
diff --git a/src/cpu/intel/smm/gen1/smmrelocate.c b/src/cpu/intel/smm/gen1/smmrelocate.c
index a5a9de3..7391ac5 100644
--- a/src/cpu/intel/smm/gen1/smmrelocate.c
+++ b/src/cpu/intel/smm/gen1/smmrelocate.c
@@ -37,10 +37,6 @@
#define G_SMRAME (1 << 3)
#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0))
-#define IA32_FEATURE_CONTROL 0x3a
-#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
-#define SMRR_ENABLE (1 << 3)
-
struct ied_header {
char signature[10];
u32 size;
diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h
index dcd23ee..f9d8f50 100644
--- a/src/include/cpu/x86/msr.h
+++ b/src/include/cpu/x86/msr.h
@@ -14,11 +14,20 @@
/* Page attribute type MSR */
#define IA32_PLATFORM_ID 0x17
+#define IA32_FEATURE_CONTROL 0x3a
+#define FEATURE_CONTROL_LOCK_BIT (1 << 0)
+#define FEATURE_ENABLE_VMX (1 << 2)
+#define SMRR_ENABLE (1 << 3)
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+#define SGX_GLOBAL_ENABLE (1 << 18)
+#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_IA32_PAT 0x277
#define IA32_BIOS_UPDT_TRIG 0x79
#define IA32_BIOS_SIGN_ID 0x8b
#define MSR_IA32_MPERF 0xe7
#define MSR_IA32_APERF 0xe8
+#define IA32_MCG_CAP 0x179
#define MSR_IA32_PM_ENABLE 0x770
#define MSR_IA32_HWP_CAPABILITIES 0x771
#define MSR_IA32_HWP_REQUEST 0x774
diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
index dcb6296..fea8686 100644
--- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc
+++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc
@@ -14,6 +14,7 @@
* GNU General Public License for more details.
*/
+#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
#include <cpu/x86/post_code.h>
@@ -35,7 +36,6 @@
#define NoEvictMod_MSR 0x2e0
#define BBL_CR_CTL3_MSR 0x11e
-#define MCG_CAP_MSR 0x179
/* Save the BIST result. */
movl %eax, %ebp
@@ -64,7 +64,7 @@
post_code(0x22)
/* Zero the variable MTRRs. */
- movl $MCG_CAP_MSR, %ecx
+ movl $IA32_MCG_CAP, %ecx
rdmsr
movzx %al, %ebx
/* First variable MTRR. */
diff --git a/src/soc/intel/broadwell/include/soc/msr.h b/src/soc/intel/broadwell/include/soc/msr.h
index 41ce17c..13cc6f2 100644
--- a/src/soc/intel/broadwell/include/soc/msr.h
+++ b/src/soc/intel/broadwell/include/soc/msr.h
@@ -18,9 +18,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define CORE_THREAD_COUNT_MSR 0x35
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
diff --git a/src/soc/intel/common/block/include/intelblocks/msr.h b/src/soc/intel/common/block/include/intelblocks/msr.h
index e1fc431..15aac62 100644
--- a/src/soc/intel/common/block/include/intelblocks/msr.h
+++ b/src/soc/intel/common/block/include/intelblocks/msr.h
@@ -17,13 +17,6 @@
#define SOC_INTEL_COMMON_MSR_H
#define MSR_CORE_THREAD_COUNT 0x35
-#define IA32_FEATURE_CONTROL 0x3a
-#define FEATURE_CONTROL_LOCK (1)
-#define FEATURE_ENABLE_VMX (1 << 2)
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
-#define SGX_GLOBAL_ENABLE (1 << 18)
-#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PLATFORM_INFO 0xce
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
/* Set MSR_PMG_CST_CONFIG_CONTROL[3:0] for Package C-State limit */
@@ -46,7 +39,6 @@
#define MSR_FEATURE_CONFIG 0x13c
#define FEATURE_CONFIG_RESERVED_MASK 0x3ULL
#define FEATURE_CONFIG_LOCK (1 << 0)
-#define IA32_MCG_CAP 0x179
#define SMM_MCA_CAP_MSR 0x17d
#define SMM_CPU_SVRSTR_BIT 57
#define SMM_CPU_SVRSTR_MASK (1 << (SMM_CPU_SVRSTR_BIT - 32))
diff --git a/src/soc/intel/common/block/sgx/sgx.c b/src/soc/intel/common/block/sgx/sgx.c
index daedcfc..6050dec 100644
--- a/src/soc/intel/common/block/sgx/sgx.c
+++ b/src/soc/intel/common/block/sgx/sgx.c
@@ -137,7 +137,7 @@
msr = rdmsr(IA32_FEATURE_CONTROL);
/* Only enable it when it is not locked */
- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {
+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {
msr.lo |= SGX_GLOBAL_ENABLE; /* Enable it */
wrmsr(IA32_FEATURE_CONTROL, msr);
}
diff --git a/src/soc/intel/common/block/vmx/vmx.c b/src/soc/intel/common/block/vmx/vmx.c
index 591ffbc..2cffdab 100644
--- a/src/soc/intel/common/block/vmx/vmx.c
+++ b/src/soc/intel/common/block/vmx/vmx.c
@@ -58,7 +58,7 @@
msr = rdmsr(IA32_FEATURE_CONTROL);
/* Only enable it when it is not locked */
- if ((msr.lo & FEATURE_CONTROL_LOCK) == 0) {
+ if ((msr.lo & FEATURE_CONTROL_LOCK_BIT) == 0) {
/* Enable VMX */
msr.lo |= FEATURE_ENABLE_VMX;
wrmsr(IA32_FEATURE_CONTROL, msr);
@@ -68,5 +68,5 @@
msr = rdmsr(IA32_FEATURE_CONTROL);
printk(BIOS_DEBUG, "VMX status: %s, %s\n",
(msr.lo & FEATURE_ENABLE_VMX) ? "enabled" : "disabled",
- (msr.lo & FEATURE_CONTROL_LOCK) ? "locked" : "unlocked");
+ (msr.lo & FEATURE_CONTROL_LOCK_BIT) ? "locked" : "unlocked");
}
diff --git a/src/soc/intel/denverton_ns/include/soc/msr.h b/src/soc/intel/denverton_ns/include/soc/msr.h
index a49e225..c816ea4 100644
--- a/src/soc/intel/denverton_ns/include/soc/msr.h
+++ b/src/soc/intel/denverton_ns/include/soc/msr.h
@@ -20,9 +20,6 @@
#define MSR_PIC_MSG_CONTROL 0x2e
#define CORE_THREAD_COUNT_MSR 0x35
-#define IA32_FEATURE_CONTROL 0x3a
-#define CPUID_VMX (1 << 5)
-#define CPUID_SMX (1 << 6)
#define MSR_PLATFORM_INFO 0xce
#define PLATFORM_INFO_SET_TDP (1 << 29)
#define MSR_PMG_CST_CONFIG_CONTROL 0xe2
diff --git a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
index af1db04..d81ed85 100644
--- a/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
+++ b/src/soc/intel/fsp_broadwell_de/include/soc/msr.h
@@ -20,7 +20,6 @@
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_PLATFORM_INFO 0xce
-#define IA32_MCG_CAP 0x179
#define IA32_PERF_CTL 0x199
#define MSR_TURBO_RATIO_LIMIT 0x1ad
#define IA32_MC0_CTL 0x400
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