Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7642
-gerrit
commit c740fd94532ed4adb45c9ec21f960a6716872a77 Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Fri Dec 5 05:01:45 2014 +1100
vendorcode/amd/agesa/f15tn: Fix GnbIommuScratch in AGESA compilation
Missing IOMMU support is missing from the libagesa Makefile, it also lacks a header with type-signature and a few bad typecast issues.
Change-Id: I7f2ad2104de9baaa66dbb6ffeb0f2b4d35fa5c16 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com Co-Author: Rudolf Marek r.marek@assembler.cz --- src/vendorcode/amd/agesa/f15tn/Makefile.inc | 1 + .../f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c | 10 +++++++++- .../f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h | 11 +++++++++++ 3 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/vendorcode/amd/agesa/f15tn/Makefile.inc b/src/vendorcode/amd/agesa/f15tn/Makefile.inc index 4b44cef..278cb8e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Makefile.inc +++ b/src/vendorcode/amd/agesa/f15tn/Makefile.inc @@ -230,6 +230,7 @@ libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieMidInitTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePostInitTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PciePowerGateTN.c libagesa-y += Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +libagesa-y += Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c libagesa-y += Proc/GNB/Modules/GnbIommuIvrs/GnbIommuIvrs.c libagesa-y += Proc/GNB/Modules/GnbIvrsLib/GnbIvrsLib.c libagesa-y += Proc/GNB/Modules/GnbMSocketLib/GnbMSocketLib.c diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c index 5ed82bc..6869ab9 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.c @@ -36,6 +36,8 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+#include "GnbIommuScratch.h" + #include "AGESA.h" #include "Ids.h" #include "S3SaveState.h" @@ -83,8 +85,14 @@ GnbIommuScratchMemoryRangeInterface ( return AGESA_FATAL; }
- AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; +/*Align the address to 64 bytes boundary */ +#ifdef __x86_64__ + AddressLow = (((UINT32) ((UINT64) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; AddressHigh = ((UINT32) (((UINT64) AllocHeapParams.BufferPtr) >> 32)) & D0F0x98_x26_IOMMUUrAddr_39_32__MASK; +#else + AddressLow = ((((UINT32) AllocHeapParams.BufferPtr)) + 0x3F) & D0F0x98_x27_IOMMUUrAddr_31_6__MASK; + AddressHigh = 0; +#endif
GnbHandle = GnbGetHandle (StdHeader); while (GnbHandle != NULL) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h new file mode 100644 index 0000000..a01b167 --- /dev/null +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbIommuScratch/GnbIommuScratch.h @@ -0,0 +1,11 @@ +#ifndef _GNBIOMMUSCRATCH_H_ +#define _GNBIOMMUSCRATCH_H_ + +#include "AGESA.h" + +AGESA_STATUS +GnbIommuScratchMemoryRangeInterface ( + IN AMD_CONFIG_PARAMS *StdHeader + ); + +#endif /* _GNBIOMMUSCRATCH_H_ */