Xi Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48073 )
Change subject: soc/mediatek/mt8192: add dramc power control ......................................................................
soc/mediatek/mt8192: add dramc power control
Controls HV or LV of VDD1/VDD2/VDDQ/VMDDR.
Signed-off-by: Xi Chen xixi.chen@mediatek.com Change-Id: I50645e3a53d5c3c9d0b1237e32fafa8745734e8a --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/dramc_pi_main.c A src/soc/mediatek/mt8192/dramc_power.c M src/soc/mediatek/mt8192/dramc_utility.c M src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h A src/soc/mediatek/mt8192/include/soc/dramc_power.h 6 files changed, 203 insertions(+), 20 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/48073/1
diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index c01d716..76a28d0 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -28,7 +28,7 @@
romstage-y += ../common/auxadc.c romstage-y += ../common/cbmem.c -romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c +romstage-y += dramc_pi_main.c dramc_pi_basic_api.c dramc_pi_calibration_api.c dramc_utility.c dramc_dvfs.c dramc_tracking.c dramc_power.c romstage-y += dramc_subsys_config.c dramc_ana_init_config.c dramc_dig_config.c romstage-y += emi.c romstage-y += flash_controller.c diff --git a/src/soc/mediatek/mt8192/dramc_pi_main.c b/src/soc/mediatek/mt8192/dramc_pi_main.c index e7c6ecb..f7bca77 100755 --- a/src/soc/mediatek/mt8192/dramc_pi_main.c +++ b/src/soc/mediatek/mt8192/dramc_pi_main.c @@ -2,9 +2,7 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> -#include <soc/pll.h> -#include <soc/pll_common.h> -#include <soc/mt6359p.h> +#include <soc/dramc_power.h>
static void dramc_write_shift_mck_write_DBI(const struct ddr_cali *cali, s8 shift_value) { @@ -209,14 +207,6 @@ } }
-static void set_vcore_voltage_for_each_freq(const struct ddr_cali *cali) -{ - u32 vcore = get_vcore_value(cali); - - dramc_info("Set DRAM vcore voltage to %u\n", vcore); - mt6359p_buck_set_voltage(MT6359P_GPU11, vcore); -} - static void get_dram_info_after_cal(struct ddr_cali *cali) { u8 vendor_id, density, max_density = 0; @@ -451,7 +441,8 @@
set_cali_datas(&cali, dparam, k_seq_idx); dramc_info("start calibration frequency %d\n", cali.frequency); - set_vcore_voltage_for_each_freq(&cali); + dramc_set_voltage(&cali); + dramc_dump_voltage(); dfs_init_for_calibration(&cali);
if (first_freq_k) @@ -485,7 +476,8 @@ dram_dfs_shu bootup_shu = get_shu_save_by_k_shu(bootup_cali_seq);
set_cali_datas(&cali, dparam, bootup_cali_seq); - set_vcore_voltage_for_each_freq(&cali); + dramc_set_voltage(&cali); + dramc_dump_voltage();
dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, DRAM_DFS_SHU1); dramc_dfs_direct_jump_sram_shu_rg_mode(&cali, bootup_shu); diff --git a/src/soc/mediatek/mt8192/dramc_power.c b/src/soc/mediatek/mt8192/dramc_power.c new file mode 100644 index 0000000..b6d1c03 --- /dev/null +++ b/src/soc/mediatek/mt8192/dramc_power.c @@ -0,0 +1,139 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/dramc_power.h> + +void __weak mainboard_set_regulator_vol(enum mtk_regulator regulator, + uint32_t voltage_uv) +{ + dramc_info("%s not implemented!\n", __func__); +} + +uint32_t __weak mainboard_get_regulator_vol(enum mtk_regulator regulator) +{ + dramc_info("%s not implemented!\n", __func__); + return 0; +} + +u32 get_vcore_value(const struct ddr_cali *cali) +{ +#ifdef HQA_HV + return cali->vcore_voltage / 100 * 105; +#elif defined(HQA_LV) + return cali->vcore_voltage / 100 * 95; +#else + return cali->vcore_voltage; +#endif +} + +u32 get_vdd1_value() +{ + return VDD1_VOL; +} + +u32 get_vdd2_value() +{ + return VDD2_VOL; +} + +u32 get_vddq_value() +{ + return VDDQ_VOL; +} + +u32 get_vmddr_value() +{ + return VMDDR_VOL; +} + +void dramc_set_vcore_voltage(const struct ddr_cali *cali) +{ + u32 vcore = get_vcore_value(cali); + + dramc_info("[%s]Set vcore voltage to %u\n", HQA_TAG, vcore); + mainboard_set_regulator_vol(MTK_REGULATOR_VCORE, vcore); +} + +void dramc_set_vdd1_voltage() +{ + u32 vdd1 = get_vdd1_value(); + + dramc_info("[%s]Set DRAM vdd1 voltage to %u\n", HQA_TAG, vdd1); + mainboard_set_regulator_vol(MTK_REGULATOR_VDD1, vdd1); +} + +void dramc_set_vdd2_voltage() +{ + u32 vdd2 = get_vdd2_value(); + + dramc_info("[%s]Set DRAM vdd2 voltage to %u\n", HQA_TAG, vdd2); + mainboard_set_regulator_vol(MTK_REGULATOR_VDD2, vdd2); +} + +void dramc_set_vddq_voltage() +{ + u32 vddq = get_vddq_value(); + + dramc_info("[%s]Set DRAM vddq voltage to %u\n", HQA_TAG, vddq); + mainboard_set_regulator_vol(MTK_REGULATOR_VDDQ, vddq); +} + +void dramc_set_vmddr_voltage() +{ + u32 vmddr = get_vmddr_value(); + + dramc_info("[%s]Set vmddr voltage to %u\n", HQA_TAG, vmddr); + mainboard_set_regulator_vol(MTK_REGULATOR_VMDDR, vmddr); +} + +u32 dramc_get_vcore_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VCORE); +} + +// TODO: use real interface +u32 dramc_get_vdd1_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD1); +} + +u32 dramc_get_vdd2_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDD2); +} + +u32 dramc_get_vddq_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VDDQ); +} + +u32 dramc_get_vmddr_voltage() +{ + return mainboard_get_regulator_vol(MTK_REGULATOR_VMDDR); +} + +void dramc_set_voltage(const struct ddr_cali *cali) +{ + dramc_set_vcore_voltage(cali); + + dramc_set_vdd1_voltage(); + dramc_set_vdd2_voltage(); + dramc_set_vddq_voltage(); + + dramc_set_vmddr_voltage(); +} + +void dramc_dump_voltage() +{ + u32 vcore, vdd1, vdd2, vddq, vmddr; + + vcore = dramc_get_vcore_voltage(); + + vdd1 = dramc_get_vdd1_voltage(); + vdd2 = dramc_get_vdd2_voltage(); + vddq = dramc_get_vddq_voltage(); + + vmddr = dramc_get_vmddr_voltage(); + dramc_info("[Dump Dram Voltage] vcore: %u, vdd1:%u, vdd2:%u, vddq:%u, vmddr:%u\n" + , vcore, vdd1, vdd2, vddq, vmddr); +} + diff --git a/src/soc/mediatek/mt8192/dramc_utility.c b/src/soc/mediatek/mt8192/dramc_utility.c old mode 100644 new mode 100755 index e8878c1..fdfbd63 --- a/src/soc/mediatek/mt8192/dramc_utility.c +++ b/src/soc/mediatek/mt8192/dramc_utility.c @@ -2,6 +2,7 @@
#include <soc/dramc_pi_api.h> #include <soc/dramc_register.h> +#include <soc/dramc_power.h> #include <soc/infracfg.h>
struct dfs_frequency_table { @@ -105,11 +106,6 @@ return cali->cbt_mode[cali->rank]; }
-u32 get_vcore_value(const struct ddr_cali *cali) -{ - return cali->vcore_voltage; -} - u32 get_frequency(const struct ddr_cali *cali) { return cali->frequency; diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h old mode 100644 new mode 100755 index e0b887a..8ac0a64 --- a/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h +++ b/src/soc/mediatek/mt8192/include/soc/dramc_pi_api.h @@ -301,7 +301,6 @@ dram_freq_grp get_freq_group_by_shu_save(dram_dfs_shu shu); dram_pinmux_type get_pinmux_type(const struct ddr_cali *cali); u32 get_frequency_by_shu(dram_dfs_shu shu); -u32 get_vcore_value(const struct ddr_cali *cali); void set_cali_datas(struct ddr_cali *cali, const struct dramc_data *dparam, dram_cali_seq k_seq); u8 get_mck2ui_div_shift(const struct ddr_cali *cali); diff --git a/src/soc/mediatek/mt8192/include/soc/dramc_power.h b/src/soc/mediatek/mt8192/include/soc/dramc_power.h new file mode 100755 index 0000000..22771e3 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/dramc_power.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_DRAMC_POWER_H__ +#define __SOC_MEDIATEK_MT8192_DRAMC_POWER_H__ + +#include <stdint.h> +#include <sys/types.h> +#include <soc/dramc_common_mt8192.h> +#include <soc/dramc_pi_api.h> +#include <soc/pll.h> +#include <soc/pll_common.h> +#include <soc/mt6359p.h> +#include <soc/regulator.h> + +#ifdef HQA_HV +#define HQA_TAG "HV" +#define VDD1_VOL 1950000 +#define VDD2_VOL 1170000 +#define VDDQ_VOL 650000 +#define VMDDR_VOL 790000 +#elif defined(HQA_LV) +#define HQA_TAG "LV" +#define VDD1_VOL 1730000 +#define VDD2_VOL 1060000 +#define VDDQ_VOL 570000 +#define VMDDR_VOL 710000 +#else // by default: HQA_NV +#define HQA_TAG "NV" +#define VDD1_VOL 1800000 +#define VDD2_VOL 1125000 +#define VDDQ_VOL 600000 +#define VMDDR_VOL 750000 +#endif + +u32 get_vcore_value(const struct ddr_cali *cali); +u32 get_vdd1_value(void); +u32 get_vdd2_value(void); +u32 get_vddq_value(void); +u32 get_vmddr_value(void); + +u32 dramc_get_vcore_voltage(void); +u32 dramc_get_vdd1_voltage(void); +u32 dramc_get_vdd2_voltage(void); +u32 dramc_get_vddq_voltage(void); +u32 dramc_get_vmddr_voltage(void); +void dramc_dump_voltage(void); + +void dramc_set_vcore_voltage(const struct ddr_cali *cali); +void dramc_set_vdd1_voltage(void); +void dramc_set_vdd2_voltage(void); +void dramc_set_vddq_voltage(void); +void dramc_set_vmddr_voltage(void); + +void dramc_set_voltage(const struct ddr_cali *cali); + +#endif /* __SOC_MEDIATEK_MT8192_DRAMC_PARAM_H__ */ +