Meera Ravindranath has uploaded this change for review.
mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree
This CL selects the PcieRpClkReqDetect for the required root ports
which is needed to allow proper clksrc gpio configuration.
BUG=None
BRANCH=None
TEST=Build and boot jslrvp with NVMe
Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
---
M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
1 file changed, 9 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/40758/1
diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
index 7dc45ae..9a06f4b 100644
--- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
+++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb
@@ -67,8 +67,17 @@
register "PcieRpEnable[1]" = "1"
register "PcieRpEnable[4]" = "1"
+ # Enable ClkReqDetect 1 for WLAN
+ # Enable ClkReqDetect 4 for NVMe
+ register "PcieRpClkReqDetect[1]" = "1"
+ register "PcieRpClkReqDetect[4]" = "1"
+
register "PcieClkSrcUsage[0]" = "0x04"
register "PcieClkSrcUsage[1]" = "0x01"
+ register "PcieClkSrcUsage[2]" = "0xFF"
+ register "PcieClkSrcUsage[3]" = "0xFF"
+ register "PcieClkSrcUsage[4]" = "0xFF"
+ register "PcieClkSrcUsage[5]" = "0xFF"
register "PcieClkSrcClkReq[0]" = "0x00"
register "PcieClkSrcClkReq[1]" = "0x01"
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