Ravi kumar has uploaded this change for review.

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sc7280: HACK PATCH: mmu configuration for ddr as bypassing qclib execution

Change-Id: I213f6063ba8a06740488f44dabf377659bb70579
---
M src/mainboard/google/herobrine/romstage.c
M src/soc/qualcomm/sc7280/mmu.c
2 files changed, 3 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/47080/1

diff --git a/src/mainboard/google/herobrine/romstage.c b/src/mainboard/google/herobrine/romstage.c
index 8844f18..9927677 100644
--- a/src/mainboard/google/herobrine/romstage.c
+++ b/src/mainboard/google/herobrine/romstage.c
@@ -6,5 +6,5 @@
 void platform_romstage_main(void)
 {
 	/* QCLib: DDR init & train */
-	qclib_load_and_run();
+	//qclib_load_and_run();
 }
diff --git a/src/soc/qualcomm/sc7280/mmu.c b/src/soc/qualcomm/sc7280/mmu.c
index 9905c29..f6e85a6 100644
--- a/src/soc/qualcomm/sc7280/mmu.c
+++ b/src/soc/qualcomm/sc7280/mmu.c
@@ -16,6 +16,8 @@
 	mmu_config_range((void *)_bsram, REGION_SIZE(bsram), CACHED_RAM);
 	mmu_config_range((void *)_dma_coherent, REGION_SIZE(dma_coherent),
 			 UNCACHED_RAM);
+	mmu_config_range((void *)_ssram, REGION_SIZE(ssram), CACHED_RAM);
+	mmu_config_range((void *)(2UL * GiB), (2UL * GiB) , CACHED_RAM);
 
 	mmu_enable();
 }

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