Hung-Te Lin uploaded patch set #3 to this change.

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util: cbfstool: Add new flag 'ALIGNED' for checking alignment at build time

Some FMAP sections (for example MRC_VAR_CACHE, RW_DDR_TRAINING, ...) are
accessed directly by raw block I/O and must be aligned at SPI flash
erase block size (see spi_flash.c#spi_flash_erase_cmd, error "SF: Erase
offset/length not multiple of erase size").

If we don't add explicit offset to these sections in FMD files, changing
size of other sections may unexpectedly cause them to be unaligned.

This patch adds a new flag "ALIGNED" so we can declare an FMAP section


to ensure the offset and size (8k) of section RW_DDR_TRAINING will be both
aligned to 4k.

Note: in current implementation the alignment is fixed at 4k, which is
supported on almost all SPI chipsets today.

TEST=Change bootblock from default.fmd to BOOTBLOCK(ALIGNED) 127k and build,
seeing error message:
"E: Section 'BOOTBLOCK'@0[0x1fc00] must be aligned to 0x1000"

Change-Id: I26b394590c28667a4afcd521c7caa2009b5b98a9
Signed-off-by: Hung-Te Lin <>
M util/cbfstool/fmap_from_fmd.c
M util/cbfstool/fmd.h
M util/cbfstool/fmd_parser.c_shipped
M util/cbfstool/fmd_parser.h_shipped
M util/cbfstool/fmd_parser.y
M util/cbfstool/fmd_scanner.c_shipped
M util/cbfstool/fmd_scanner.h_shipped
M util/cbfstool/fmd_scanner.l
8 files changed, 629 insertions(+), 440 deletions(-)

git pull ssh:// refs/changes/62/37262/3

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I26b394590c28667a4afcd521c7caa2009b5b98a9
Gerrit-Change-Number: 37262
Gerrit-PatchSet: 3
Gerrit-Owner: Hung-Te Lin <>
Gerrit-Reviewer: Arthur Heymans <>
Gerrit-Reviewer: Hung-Te Lin <>
Gerrit-Reviewer: Julius Werner <>
Gerrit-Reviewer: Yu-Ping Wu <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-MessageType: newpatchset