Martin Roth (martinroth@google.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/12337
-gerrit
commit f755ec40f70a360cc0241e26cb9e288db096df14 Author: Martin Roth martinroth@google.com Date: Thu Nov 5 12:30:06 2015 -0700
fsp1_0: fix microcode loading
This should fix microcode loading by the FSP. - Update the name of the microcode file used to find the size to allow the file generated from the .h file to be loaded. - Add CPU_MICROCODE_CBFS_LOC back to FSP 1.0 Kconfig. This is still needed for loading microcode by the FSP.
Change-Id: Ia6de09f7f4d18b03fb415eaa09dc755d3b25cdbc Signed-off-by: Martin Roth martinroth@google.com --- src/drivers/intel/fsp1_0/Kconfig | 7 +++++++ src/drivers/intel/fsp1_0/Makefile.inc | 4 ++-- 2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/drivers/intel/fsp1_0/Kconfig b/src/drivers/intel/fsp1_0/Kconfig index 36bfa7c..5610eba 100644 --- a/src/drivers/intel/fsp1_0/Kconfig +++ b/src/drivers/intel/fsp1_0/Kconfig @@ -36,6 +36,13 @@ config DCACHE_RAM_SIZE
if HAVE_FSP_BIN
+config CPU_MICROCODE_CBFS_LOC + hex "Microcode update base address in CBFS" + default 0 + help + The location (base address) in CBFS that contains the microcode update + binary. + config FSP_FILE string "Intel FSP binary path and filename" help diff --git a/src/drivers/intel/fsp1_0/Makefile.inc b/src/drivers/intel/fsp1_0/Makefile.inc index aac832b..e62047e 100644 --- a/src/drivers/intel/fsp1_0/Makefile.inc +++ b/src/drivers/intel/fsp1_0/Makefile.inc @@ -21,8 +21,8 @@ romstage-$(CONFIG_ENABLE_MRC_CACHE) += fastboot_cache.c
CPPFLAGS_common += -Isrc/drivers/intel/fsp1_0 -I$(objgenerated)
-ifneq ($(cpu_microcode_bins),) -$(objgenerated)/microcode_size.h: $(obj)/cpu_microcode_blob.bin +ifneq ($(cpu_microcode_blob.bin-file),) +$(objgenerated)/microcode_size.h: $(cpu_microcode_blob.bin-file) printf "#define MICROCODE_REGION_LENGTH $(call file-size,$<)" > $@.tmp \ && cmp $@.tmp $@ 2>/dev/null || mv $@.tmp $@ else