Arthur Heymans uploaded patch set #10 to this change.

View Change

cpu/x86/cache: CLFLUSH programs to memory before running

When cbmem is initialized in romstage and postcar placed in the stage
cache + cbmem where it is run, the assumption is made that these are
all in UC memory such that calling INVD in postcar is OK.

For performance reasons (e.g. postcar decompression) it is desirable
to cache cbmem and the stage cache during romstage.

Another reason is that AGESA sets up MTRR during romstage to cache all
dram, which is currently worked around by using additional MTRR's to
make that UC.

TESTED on ASUS P5QL-EM on both regular and S3 resume bootpath.

Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Signed-off-by: Arthur Heymans <>
M src/arch/x86/postcar_loader.c
M src/cpu/x86/Kconfig
M src/cpu/x86/cache/
M src/cpu/x86/cache/cache.c
M src/include/cpu/x86/cache.h
5 files changed, 77 insertions(+), 0 deletions(-)

git pull ssh:// refs/changes/96/37196/10

To view, visit change 37196. To unsubscribe, or for help writing mail filters, visit settings.

Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I7ff2a57aee620908b71829457ea0f5a0c410ec5b
Gerrit-Change-Number: 37196
Gerrit-PatchSet: 10
Gerrit-Owner: Arthur Heymans <>
Gerrit-Reviewer: Arthur Heymans <>
Gerrit-Reviewer: Marshall Dawson <>
Gerrit-Reviewer: Martin Roth <>
Gerrit-Reviewer: Patrick Georgi <>
Gerrit-Reviewer: Subrata Banik <>
Gerrit-Reviewer: build bot (Jenkins) <>
Gerrit-CC: Aaron Durbin <>
Gerrit-CC: Paul Menzel <>
Gerrit-MessageType: newpatchset