Duncan Laurie (dlaurie@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12793
-gerrit
commit 61de8284ac7901ab6af81d763dc27b29fa67b950 Author: Duncan Laurie dlaurie@google.com Date: Tue Dec 22 17:09:16 2015 -0800
broadwell: Fix SATA Gen3 DTLE configuration registers
The port0 and port1 registers were swapped, which meant it did not work to apply the DTLE settings to the correct SATA port.
Change-Id: Ifb8890a563a741129ec8ddf72e73ab021c7d33da Signed-off-by: Duncan Laurie dlaurie@google.com --- src/soc/intel/broadwell/include/soc/sata.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/soc/intel/broadwell/include/soc/sata.h b/src/soc/intel/broadwell/include/soc/sata.h index 987bc3c..d1aa45d 100644 --- a/src/soc/intel/broadwell/include/soc/sata.h +++ b/src/soc/intel/broadwell/include/soc/sata.h @@ -27,10 +27,10 @@ #define SATA_SECRT88_VADJ_MASK 0xff #define SATA_SECRT88_VADJ_SHIFT 16
-#define SATA_IOBP_SP0DTLE_DATA 0xea002550 -#define SATA_IOBP_SP0DTLE_EDGE 0xea002554 -#define SATA_IOBP_SP1DTLE_DATA 0xea002750 -#define SATA_IOBP_SP1DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP0DTLE_DATA 0xea002750 +#define SATA_IOBP_SP0DTLE_EDGE 0xea002754 +#define SATA_IOBP_SP1DTLE_DATA 0xea002550 +#define SATA_IOBP_SP1DTLE_EDGE 0xea002554
#define SATA_DTLE_MASK 0xF #define SATA_DTLE_DATA_SHIFT 24