4 comments:
File src/cpu/allwinner/a10/ram_segs.h:
Patch Set #10, Line 27: << 20
Seen this more often, maybe worth to trigger a follow up to replace […]
I'll do that.
/*
* By CBFS cache, we mean a cached copy, in RAM, of the entire CBFS region.
*/
static inline uintptr_t a1x_get_cbfs_cache_top(void)
{
/* Arbitrary 16 MiB gap for cbmem tables and bouncebuffer */
return a1x_get_cbmem_top() - (16 << 20);
}
static inline uintptr_t a1x_get_cbfs_cache_base(void)
{
return a1x_get_cbfs_cache_top() - CONFIG_ROM_SIZE;
}
I was wondering why we don't have to update any caller... […]
this cpu/soc code was actually never completed. The code that would allow it to read cbfs from the bootmedium (typically SD/emmc) was never pushed for review, so it won't get past the bootblock (raminit is done in there).
File src/drivers/intel/fsp1_1/raminit.c:
Patch Set #10, Line 155: (unsigned int)
or use PRIxPTR instead
that macro is not implemented in coreboot.
File src/mainboard/emulation/qemu-power8/cbmem.c:
Patch Set #10, Line 21: /* For now, last 1M of 4G */
Is this a lie? CBMEM will be *below* the last 1MiB...
looks quite weird indeed.
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