Subrata Banik submitted this change.

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Approvals: build bot (Jenkins): Verified Mario Scheithauer: Looks good to me, but someone else must approve Angel Pons: Looks good to me, approved Michael Niewöhner: Looks good to me, approved 
apollolake boards: Enable CSE in devicetree

Enable CSE PCI device Bus 0: Device 0x0f: Function 0x00 to let
Intel common cse block code can use this device.

Calling me_read_config32(offset) function from ramstage:

Without this CL :
HECI: Global Reset(Type:1) Command
BUG: me_read_config32 requests hidden 00:0f.0
PCI: dev is NULL!

With this CL :
HECI: Global Reset(Type:1) Command
HECI: Global Reset success!

Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45469
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
---
M src/mainboard/google/reef/variants/baseboard/devicetree.cb
M src/mainboard/google/reef/variants/coral/devicetree.cb
M src/mainboard/google/reef/variants/pyro/devicetree.cb
M src/mainboard/google/reef/variants/sand/devicetree.cb
M src/mainboard/google/reef/variants/snappy/devicetree.cb
M src/mainboard/intel/apollolake_rvp/devicetree.cb
M src/mainboard/intel/leafhill/devicetree.cb
M src/mainboard/intel/minnow3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
M src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
M src/mainboard/up/squared/devicetree.cb
15 files changed, 15 insertions(+), 1 deletion(-)

diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
index 4c35bd2..da80b8e 100644
--- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb
+++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb
@@ -139,6 +139,7 @@
 				device generic 0 on end
 			end
 		end
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/coral/devicetree.cb b/src/mainboard/google/reef/variants/coral/devicetree.cb
index f987e1d..f2fc3a6 100644
--- a/src/mainboard/google/reef/variants/coral/devicetree.cb
+++ b/src/mainboard/google/reef/variants/coral/devicetree.cb
@@ -139,6 +139,7 @@
 				device generic 0 on end
 			end
 		end
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb
index 1282edb..920431b 100644
--- a/src/mainboard/google/reef/variants/pyro/devicetree.cb
+++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb
@@ -148,6 +148,7 @@
 				device generic 0 on end
 			end
 		end
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/sand/devicetree.cb b/src/mainboard/google/reef/variants/sand/devicetree.cb
index ad76a91..aba1227 100644
--- a/src/mainboard/google/reef/variants/sand/devicetree.cb
+++ b/src/mainboard/google/reef/variants/sand/devicetree.cb
@@ -135,6 +135,7 @@
 				device generic 0 on end
 			end
 		end
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb
index a82400f..ad8c808 100644
--- a/src/mainboard/google/reef/variants/snappy/devicetree.cb
+++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb
@@ -144,6 +144,7 @@
 				device generic 0 on end
 			end
 		end
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 off end	# - SATA
 		device pci 13.0 off end	# - Root Port 2 - PCIe-A 0
diff --git a/src/mainboard/intel/apollolake_rvp/devicetree.cb b/src/mainboard/intel/apollolake_rvp/devicetree.cb
index f7e82a0..dd12a5b 100644
--- a/src/mainboard/intel/apollolake_rvp/devicetree.cb
+++ b/src/mainboard/intel/apollolake_rvp/devicetree.cb
@@ -22,6 +22,7 @@
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0
diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/leafhill/devicetree.cb
+++ b/src/mainboard/intel/leafhill/devicetree.cb
@@ -22,6 +22,7 @@
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0
diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb
index 6c872b1..e2f2f8e 100644
--- a/src/mainboard/intel/minnow3/devicetree.cb
+++ b/src/mainboard/intel/minnow3/devicetree.cb
@@ -22,6 +22,7 @@
 		device pci 0d.2 on end	# - SPI
 		device pci 0d.3 on end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
+		device pci 0f.0 on end	# - CSE
 		device pci 11.0 on end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
index 0e72fcf..2e43648 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/devicetree.cb
@@ -69,6 +69,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0 - MACPHY
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
index bee531f..1ac551a 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/devicetree.cb
@@ -61,6 +61,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
index e1e79b4..bc5a9cf 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/devicetree.cb
@@ -57,6 +57,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
index be50408..7e51666 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl4/devicetree.cb
@@ -58,6 +58,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
index 33664fe..b5fb33b 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/devicetree.cb
@@ -60,6 +60,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
index a865f9f..4aa8bc9 100644
--- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
+++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/devicetree.cb
@@ -28,6 +28,7 @@
 		device pci 0d.2 on  end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on  end	# - Audio
+		device pci 0f.0 on  end	# - CSE
 		device pci 11.0 on  end	# - ISH
 		device pci 12.0 on  end	# - SATA
 		device pci 13.0 on  end	# - RP 2 - PCIe A 0
diff --git a/src/mainboard/up/squared/devicetree.cb b/src/mainboard/up/squared/devicetree.cb
index da2ff06..417d039 100644
--- a/src/mainboard/up/squared/devicetree.cb
+++ b/src/mainboard/up/squared/devicetree.cb
@@ -34,7 +34,7 @@
 		device pci 0d.2 off end	# - SPI
 		device pci 0d.3 off end	# - Shared SRAM
 		device pci 0e.0 on end	# - Audio
-		device pci 0f.0 on end  # - TXE
+		device pci 0f.0 on end	# - TXE
 		device pci 11.0 off end	# - ISH
 		device pci 12.0 on end	# - SATA
 		device pci 13.0 on end	# - PCIe-A 1 - PcieRootPort[2]

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I97d221ae52b4b03ecd859d708847ad77fe4bf465
Gerrit-Change-Number: 45469
Gerrit-PatchSet: 6
Gerrit-Owner: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Elyes HAOUAS
Gerrit-Reviewer: Furquan Shaikh <furquan.m.shaikh@gmail.com>
Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer@siemens.com>
Gerrit-Reviewer: Michael Niewöhner <foss@mniewoehner.de>
Gerrit-Reviewer: Nico Huber <nico.h@gmx.de>
Gerrit-Reviewer: Subrata Banik <subrata.banik@intel.com>
Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak@chromium.org>
Gerrit-Reviewer: Werner Zeh <werner.zeh@siemens.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-CC: Subrata Banik <subi.banik@gmail.com>
Gerrit-MessageType: merged