Angel Pons has uploaded this change for review.

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sb/intel/lynxpoint: Use correct port mask for LPT-LP

Lynxpoint LP only has 4 SATA ports.

Change-Id: I565a0b2d29ac8fff8b5d87e0f1dbb3667f229365
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/southbridge/intel/lynxpoint/sata.c
1 file changed, 9 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/47035/1

diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c
index 167f4df..f4ad6cd 100644
--- a/src/southbridge/intel/lynxpoint/sata.c
+++ b/src/southbridge/intel/lynxpoint/sata.c
@@ -12,6 +12,12 @@
 #include "iobp.h"
 #include "pch.h"
 
+#if CONFIG(INTEL_LYNXPOINT_LP)
+#define SATA_PORT_MASK	0x0f
+#else
+#define SATA_PORT_MASK	0x3f
+#endif
+
 typedef struct southbridge_intel_lynxpoint_config config_t;
 
 static inline u32 sir_read(struct device *dev, int idx)
@@ -95,7 +101,7 @@
 	pci_write_config16(dev, IDE_TIM_SEC, IDE_DECODE_ENABLE);
 
 	/* for AHCI, Port Enable is managed in memory mapped space */
-	pci_update_config16(dev, 0x92, ~0x3f, 0x8000 | config->sata_port_map);
+	pci_update_config16(dev, 0x92, ~SATA_PORT_MASK, 0x8000 | config->sata_port_map);
 	udelay(2);
 
 	/* Setup register 98h */
@@ -121,7 +127,7 @@
 
 	/* SATA Initialization register */
 	reg32 = 0x183;
-	reg32 |= (config->sata_port_map ^ 0x3f) << 24;
+	reg32 |= (config->sata_port_map ^ SATA_PORT_MASK) << 24;
 	reg32 |= (config->sata_devslp_mux & 1) << 15;
 	pci_write_config32(dev, 0x94, reg32);
 
@@ -241,7 +247,7 @@
 	 * Set SATA controller mode early so the resource allocator can
 	 * properly assign IO/Memory resources for the controller.
 	 */
-	pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ 0x3f) << 8);
+	pci_write_config16(dev, 0x90, 0x0060 | (config->sata_port_map ^ SATA_PORT_MASK) << 8);
 }
 
 static struct device_operations sata_ops = {

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