Patch Set 5:
Patch Set 5:
I had a brief look in the SIO datasheet and it states that it (as expected) either uses the IO port pair 0x2e/0x2f or 0x4e/0x4f
These are the control/index ports (and the main logical device id) of the SuperIO. They should be correct. Otherwise all other subdevices (LDNs) wouldn't work either.
I rather think the HWM is working already. Its just the memory area where it places the values seems wrong. Superiotool.log shows 0x09 for all values but h/w fan/temp control seems to work properly nevertheless. I think the autoported 0x00fc0295 address in romstage.c is wrong.
Ah, ok, for the HWM part. There you need to set the IO address for that LDN and possibly adapt the LPC IO decode ranges for the chipset. That part is documented in the southbridge datasheet.
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