Jonathan Zhang uploaded patch set #2 to this change.

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soc/intel/xeon_sp/skx: fix mem64 BAR assignment

PCIe End Point device's BARS need to be accomondated in bridge device's
resource base/limit config registers. In particular, mem32/mem64
(non-prefetchable) BARs need to be accomondated in bridge device's
mem base/limit config registers.

This patches fixes the bug that mem64 BAR is not considered when
setting bridge device's mem base/limit config registers.

Without this patch, TiogaPass without riser card works fine; but on
TiogaPass with riser card, the boot fails with MTRR table overflow.

While at this, optimized the code, and also taken into account
whether FSP HOB indicates that mem32 address space is used for
PCIe mem64 allocation or not.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Signed-off-by: Reddy Chagam <anjaneya.chagam@intel.com>
Tested-by: Morgan_Jang@wiwynn.com
Tested-by: Ryback.Hung@quantatw.com
Change-Id: I8dd7d94d52ad02f22c8e69b2e5d6dde2a79bc1f7
---
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h
M src/soc/intel/xeon_sp/skx/soc_util.c
3 files changed, 115 insertions(+), 97 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/40500/2

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