Jes Klinke would like Jes Klinke to review this change.
mb/google/volteer: Skip TPM detection except on SPI
Production Volteer devices have Cr50 TPM connected via SPI, depending on
Cr50 firmware version it may or may not support long enough interrupt
pulses for the SoC to safely be able to enable lowest power mode.
Some reworked Volteer devices have had the Cr50 (Haven) TPM replaced
with Dauntless, communicating via I2C. The I2C drivers do not support
being accessed early in ramstage, before chip init and memory
mapping, (tlcl_lib_init() will halt with an error finding the I2C
controlled base address.)
Since the Dauntless device under development can be made to support
longer interrupts, or a completely new interrupt signalling mode, there
is no need to try to go through the same discovery as is done via SPI.
This CL will skip the discovery, enabling the S0i3.4 sleep mode in all
cases, on the reworked test devices.
BUG=b:169526865
TEST=abuild -t GOOGLE_VOLTEER2 -c max -x
Change-Id: I08a533cede30a3c0ab943938961dc7e4b572d4ce
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
---
M 3rdparty/amd_blobs
M src/mainboard/google/volteer/mainboard.c
2 files changed, 13 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/47049/1
diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs
index 8c668ab..e393a88 160000
--- a/3rdparty/amd_blobs
+++ b/3rdparty/amd_blobs
@@ -1 +1 @@
-Subproject commit 8c668ab552a02724a07f8c6e7285a5f21a61569b
+Subproject commit e393a885c89f8ee3f05242a9e42578c60931b49d
diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c
index b4d6676..480a3f6 100644
--- a/src/mainboard/google/volteer/mainboard.c
+++ b/src/mainboard/google/volteer/mainboard.c
@@ -45,13 +45,24 @@
void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *cfg)
{
int ret;
+ if (!CONFIG(MAINBOARD_HAS_SPI_TPM_CR50)) {
+ /*
+ * Negotiation of long interrupt pulses is only supported via
+ * SPI. I2C is only used on reworked prototypes on which the
+ * TPM is replaced with Dauntless under development, it will
+ * use long pulses by default, or use the interrupt line in a
+ * different way altogether.
+ */
+ return;
+ }
+
ret = tlcl_lib_init();
if (ret != VB2_SUCCESS) {
printk(BIOS_ERR, "tlcl_lib_init() failed: 0x%x\n", ret);
return;
}
- if (CONFIG(MAINBOARD_HAS_SPI_TPM_CR50) && cr50_is_long_interrupt_pulse_enabled()) {
+ if (cr50_is_long_interrupt_pulse_enabled()) {
printk(BIOS_INFO, "Enabling S0i3.4\n");
} else {
/*
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