Attention is currently required from: Hung-Te Lin.
Rex-BC Chen has uploaded this change for review.
soc/medaitek/mt8186: set pin drive strength to 8mA for NOR
Set NOR pin drive to 8mA to comply with HW requirement.
This implementation is according to chapter 5.1, 5.6 and 5.8 in MT8186
Functional Specification.
BUG=b:218775654, b:216462313, b:212375511
TEST=SPI SI tests for AP to NOR pass for both kingler and krabby.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I5b6e37b0f7d4207ea35f11394d25ad1e096ac01a
---
M src/soc/mediatek/mt8186/spi.c
1 file changed, 11 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/62472/1
diff --git a/src/soc/mediatek/mt8186/spi.c b/src/soc/mediatek/mt8186/spi.c
index d4d3684..f7a376d 100644
--- a/src/soc/mediatek/mt8186/spi.c
+++ b/src/soc/mediatek/mt8186/spi.c
@@ -6,6 +6,7 @@
*/
#include <assert.h>
+#include <console/console.h>
#include <device/mmio.h>
#include <spi_flash.h>
#include <soc/addressmap.h>
@@ -13,6 +14,8 @@
#include <soc/gpio.h>
#include <soc/spi.h>
+#define NOR_PIN_DRIVE_STRENTH GPIO_DRV3
+
struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = {
{
.regs = (void *)SPI0_BASE,
@@ -147,6 +150,14 @@
for (size_t i = 0; i < ARRAY_SIZE(nor_pinmux[gpio_set]); i++) {
gpio_set_pull(ptr[i].gpio, GPIO_PULL_ENABLE, ptr[i].select);
gpio_set_mode(ptr[i].gpio, ptr[i].func);
+
+ /* Set pin drive to GPIO_DRV3 which is defined as 8mA in MT8186 */
+ if (gpio_set_driving(ptr[i].gpio, NOR_PIN_DRIVE_STRENTH) < 0)
+ printk(BIOS_WARNING, "%s: failed to set pin drive for %d\n",
+ __func__, ptr[i].gpio.id);
+ else
+ printk(BIOS_INFO, "%s: got pin drive: %#x\n", __func__,
+ gpio_get_driving(ptr[i].gpio));
}
}
To view, visit change 62472. To unsubscribe, or for help writing mail filters, visit settings.