Subrata Banik uploaded patch set #2 to this change.

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soc/intel/common/systemagent: Add SOC_INTEL_COMMON_BLOCK_SA_VERSION_2

System Agent (SA) register 0x60:PCIEXBAR register LENGTH offset definition has
been changed for newer SoC. This change provides a new Kconfig option that
can be selected by SoCs using these new bit definitions of LENGTH. Common code
takes care of setting the right value for pciex length depending upon the version
selected by SOC.

TEST=DSDT dump shows PCIEXBAR.LENGTH offset (3:1) for TGL

Change-Id: Ifa00c4e6b872896ace975f1c6bd56c6efb172410
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
---
M src/soc/intel/common/block/acpi/acpi/northbridge.asl
M src/soc/intel/common/block/systemagent/Kconfig
M src/soc/intel/common/block/systemagent/systemagent_def.h
M src/soc/intel/common/block/systemagent/systemagent_early.c
4 files changed, 62 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/38456/2

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