Jonathan Neuschäfer has uploaded this change for review.

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arch/riscv: Drop mret workaround

Our toolchain can compile mret now, and once the encoding changes, we'll
have to adjust the code anyway.

Change-Id: Ic37a849f65195006fa15d74f651a8aa9a9da5b5c
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
---
M src/arch/riscv/payload.S
M src/arch/riscv/trap_util.S
2 files changed, 3 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/21762/1

diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S
index ce88bc3..a189adf 100644
--- a/src/arch/riscv/payload.S
+++ b/src/arch/riscv/payload.S
@@ -24,7 +24,4 @@
 	li t2,  (1<<11)
 	or t0, t0, t2
 	csrw mstatus, t0
-
-	// We're still in toolchain no mans land.
-	.word 0x30200073
-	//mret
+	mret
diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S
index ae32379..44cfab7 100644
--- a/src/arch/riscv/trap_util.S
+++ b/src/arch/riscv/trap_util.S
@@ -141,10 +141,10 @@
   csrr a0, mscratch
   restore_regs
   # go back into supervisor call
-  .word 0x30200073 # mret
+  mret
   .global machine_call_return
 machine_call_return:
     csrr a0, mscratch
     restore_regs
     # go back into machine call
-    .word 0x30200073 # mret
+    mret

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