Felix Held would like Martin Roth and Rob Barnes to review this change.
soc/amd/picasso: Cleanup legacy UART config
Cleaned up configuration of the legacy UART.
Added Kconfig options for the mapping between UART
and legacy I/O decode.
TEST=Manual, boot trembyle, verify UART configured correctly in log.
serial8250: ttyS3 at I/O 0x2e8 (IRQ = 3, base_baud = 115200) is
a 16550A
$ io_write8 0x2e8 97 -> a is output on console
BUG=b:143283592
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Id08ff6428d4019303ebb6e44e13aba480cf1fde2
Reviewed-on: https://chromium-review.googlesource.com/2037891
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Martin Roth <martinroth@google.com>
---
M src/soc/amd/picasso/Kconfig
M src/soc/amd/picasso/include/soc/southbridge.h
M src/soc/amd/picasso/southbridge.c
M src/soc/amd/picasso/uart.c
4 files changed, 39 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/40322/1
diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig
index d9211b4..8279fd8 100644
--- a/src/soc/amd/picasso/Kconfig
+++ b/src/soc/amd/picasso/Kconfig
@@ -157,6 +157,7 @@
config PICASSO_UART_LEGACY
bool "Decode legacy I/O range"
+ default n
depends on PICASSO_UART
help
Assign I/O 3F8, 2F8, etc. to a Picasso UART. Only a single UART may
@@ -164,6 +165,19 @@
console. A UART accessed with I/O does not allow all the features
of MMIO. The MMIO decode is still present when this option is used.
+config PICASSO_UART_LEGACY_RANGE
+ int "Console uart legacy I/O range"
+ depends on PICASSO_UART_LEGACY
+ range 0 3
+ default 0
+ help
+ Assign legacy I/O range to the Picasso console UART.
+ Possible I/O ranges:
+ 0: 2e8
+ 1: 2f8
+ 2: 3e8
+ 3: 3f8
+
config CONSOLE_UART_BASE_ADDRESS
depends on CONSOLE_SERIAL && PICASSO_UART
hex
diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h
index a134245..3c13711 100644
--- a/src/soc/amd/picasso/include/soc/southbridge.h
+++ b/src/soc/amd/picasso/include/soc/southbridge.h
@@ -226,10 +226,8 @@
#define FCH_AOAC_STAT0 BIT(6)
#define FCH_AOAC_STAT1 BIT(7)
-#define FCH_UART_LEGACY_DECODE 0xfedc0020
-#define FCH_LEGACY_3F8_SH 3
-#define FCH_LEGACY_2F8_SH 1
-#define FCH_LEGACY_3E8_SH 2
+#define FCH_LEGACY_UART_DECODE 0xfedc0020
+#define FCH_LEGACY_UART_WHICH_SHIFT 8
#define PM1_LIMIT 16
#define GPE0_LIMIT 28
@@ -322,6 +320,7 @@
void fch_pre_init(void);
void fch_early_init(void);
void set_uart_config(int idx);
+void set_uart_legacy_config(int uart_idx, int range_idx);
/* Initialize all the i2c buses that are marked with early init. */
void i2c_soc_early_init(void);
diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c
index 6bedab0..fa3a71c 100644
--- a/src/soc/amd/picasso/southbridge.c
+++ b/src/soc/amd/picasso/southbridge.c
@@ -276,6 +276,9 @@
sb_reset_i2c_slaves();
if (CONFIG(PICASSO_UART))
set_uart_config(CONFIG_UART_FOR_CONSOLE);
+ if (CONFIG(PICASSO_UART_LEGACY))
+ set_uart_legacy_config(CONFIG_UART_FOR_CONSOLE,
+ CONFIG_PICASSO_UART_LEGACY_RANGE);
}
static void print_num_status_bits(int num_bits, uint32_t status,
diff --git a/src/soc/amd/picasso/uart.c b/src/soc/amd/picasso/uart.c
index 14a43c1..38e0865 100644
--- a/src/soc/amd/picasso/uart.c
+++ b/src/soc/amd/picasso/uart.c
@@ -39,10 +39,28 @@
return uart_info[idx].base;
}
+
+void set_uart_legacy_config(int uart_idx, int range_idx)
+{
+ uint16_t uart_leg;
+ uint8_t uart_leg_which_offset;
+
+ if (uart_idx < 0 || uart_idx > 3 || range_idx < 0 || range_idx > 3)
+ return;
+
+ uart_leg = read16((void *)FCH_LEGACY_UART_DECODE);
+ /* Map uart_idx to io range_idx */
+ uart_leg_which_offset = range_idx * 2 + FCH_LEGACY_UART_WHICH_SHIFT;
+ uart_leg &= ~(0x3 << uart_leg_which_offset);
+ uart_leg |= uart_idx << uart_leg_which_offset;
+ /* Enable io range */
+ uart_leg |= 1 << range_idx;
+ write16((void *)FCH_LEGACY_UART_DECODE, uart_leg);
+}
+
void set_uart_config(int idx)
{
uint32_t uart_ctrl;
- uint16_t uart_leg;
if (idx < 0 || idx > ARRAY_SIZE(uart_info))
return;
@@ -55,20 +73,6 @@
sm_pci_write32(SMB_UART_CONFIG, uart_ctrl);
}
- if (CONFIG(PICASSO_UART_LEGACY) && idx != 3) {
- /* Force 3F8 if idx=0, 2F8 if idx=1, 3E8 if idx=2 */
-
- /* TODO: make clearer once PPR is updated */
- uart_leg = (idx << 8) | (idx << 10) | (idx << 12) | (idx << 14);
- if (idx == 0)
- uart_leg |= 1 << FCH_LEGACY_3F8_SH;
- else if (idx == 1)
- uart_leg |= 1 << FCH_LEGACY_2F8_SH;
- else if (idx == 2)
- uart_leg |= 1 << FCH_LEGACY_3E8_SH;
-
- write16((void *)FCH_UART_LEGACY_DECODE, uart_leg);
- }
}
unsigned int uart_platform_refclk(void)
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