[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Add required FSP UPD changes for CML

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31284 )

Change subject: soc/intel/cannonlake: Add required FSP UPD changes for CML
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Patch Set 7:

(3 comments)

https://review.coreboot.org/#/c/31284/7/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/31284/7/src/soc/intel/cannonlake/fsp_params.... 
PS7, Line 38: 	memcpy(params->SerialIoI2cMode, config->SerialIoI2cMode, CONFIG_SOC_INTEL_I2C_DEV_MAX);
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https://review.coreboot.org/#/c/31284/7/src/soc/intel/cannonlake/fsp_params.... 
PS7, Line 39: 	memcpy(params->SerialIoSpiMode, config->SerialIoGSpiMode, CONFIG_SOC_INTEL_COMMON_BLOCK_GSPI_MAX);
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https://review.coreboot.org/#/c/31284/7/src/soc/intel/cannonlake/fsp_params.... 
PS7, Line 40: 	memcpy(params->SerialIoUartMode, config->SerialIoUartMode, SOC_INTEL_CML_UART_DEV_MAX);
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