Patch Set 12:

Patch Set 12:

I have recently noticed that after apu2 migration to postcar the MTRRs became inconsistent across all cores. The APs have an additional UC entry probably for cbmem?, which stays programmed up to the CPU init in ramstage. Since the postcar frame is built only from WB entries, the BSP has one entry less than APs which causes this inconsistence. Would this patch resolve this issue? Or is this something different?

Anyway I will test this.

Inconsistent MTRR is acceptable for a short amount of time like during the firmware. If the MTRRs are still incosistent when Linux boots that generally results in hangs.

Postcar (which is in dmar/cbmem) invalidates cache so it must hit dram before that. Making cbmem UC makes that possible but CLFLUSHing it to RAM (if possible) is a cleaner solution. It might also result in (small) boot speedups. This patch would indeed avoid making an UC MTRR 'hole' for cbmem.

There must be something in AGESA that still sets the UC entries, keep getting the inconsistent MTRRs (but Linux fixes it by itself.) I will reinvestigate this and probably the uC mapping can be dropped for APs (IIRC it's 1MB from the top of RAM).

Patch set 12:Code-Review +1

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