Wim Vervoorn has uploaded this change for review.
soc/intel/skylake: Remove misleading BUG: messages
The skylake pch_log_rp_wake_source function causes a "BUG:
pch_log_rp_wake_source requests hidden...." message for each root port
not listed in the device tree. This is caused by the fact that the
function tries to read all root ports possible on the Skylake PCH. This
is required because of a flaw in the PCH.
The issue is solved by using the 'pcidev_path_on_root' function instead
of the one that is standard for the Skylake SoC. This routine doesn
display the "BUG" messages.
BUG=N/A
TEST=build
Change-Id: I6bc04e48e97b0a29aef8aa050d3aad116cff1a14
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
---
M src/soc/intel/skylake/elog.c
1 file changed, 59 insertions(+), 24 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/38750/1
diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c
index 411b3e9..a3c8fc4 100644
--- a/src/soc/intel/skylake/elog.c
+++ b/src/soc/intel/skylake/elog.c
@@ -120,6 +120,41 @@
}
#define RP_PME_STS_BIT (1 << 16)
+
+#if !defined(__SIMPLE_DEVICE__)
+//#include <device/device.h>
+#define RP_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
+#else
+#define RP_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
+#endif
+
+#define RP_DEV_PCIE1 RP_DEV(PCIE, 0)
+#define RP_DEV_PCIE2 RP_DEV(PCIE, 1)
+#define RP_DEV_PCIE3 RP_DEV(PCIE, 2)
+#define RP_DEV_PCIE4 RP_DEV(PCIE, 3)
+#define RP_DEV_PCIE5 RP_DEV(PCIE, 4)
+#define RP_DEV_PCIE6 RP_DEV(PCIE, 5)
+#define RP_DEV_PCIE7 RP_DEV(PCIE, 6)
+#define RP_DEV_PCIE8 RP_DEV(PCIE, 7)
+
+#define RP_DEV_PCIE9 RP_DEV(PCIE_1, 0)
+#define RP_DEV_PCIE10 RP_DEV(PCIE_1, 1)
+#define RP_DEV_PCIE11 RP_DEV(PCIE_1, 2)
+#define RP_DEV_PCIE12 RP_DEV(PCIE_1, 3)
+#define RP_DEV_PCIE13 RP_DEV(PCIE_1, 4)
+#define RP_DEV_PCIE14 RP_DEV(PCIE_1, 5)
+#define RP_DEV_PCIE15 RP_DEV(PCIE_1, 6)
+#define RP_DEV_PCIE16 RP_DEV(PCIE_1, 7)
+
+#define RP_DEV_PCIE17 RP_DEV(PCIE_2, 0)
+#define RP_DEV_PCIE18 RP_DEV(PCIE_2, 1)
+#define RP_DEV_PCIE19 RP_DEV(PCIE_2, 2)
+#define RP_DEV_PCIE20 RP_DEV(PCIE_2, 3)
+#define RP_DEV_PCIE21 RP_DEV(PCIE_2, 4)
+#define RP_DEV_PCIE22 RP_DEV(PCIE_2, 5)
+#define RP_DEV_PCIE23 RP_DEV(PCIE_2, 6)
+#define RP_DEV_PCIE24 RP_DEV(PCIE_2, 7)
+
static void pch_log_rp_wake_source(void)
{
size_t i, maxports;
@@ -131,30 +166,30 @@
uint32_t val;
struct pme_status_info pme_status_info[] = {
- { PCH_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },
- { PCH_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },
- { PCH_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },
- { PCH_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },
- { PCH_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },
- { PCH_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },
- { PCH_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },
- { PCH_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },
- { PCH_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },
- { PCH_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },
- { PCH_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },
- { PCH_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },
- { PCH_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 },
- { PCH_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 },
- { PCH_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 },
- { PCH_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 },
- { PCH_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 },
- { PCH_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 },
- { PCH_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 },
- { PCH_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 },
- { PCH_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 },
- { PCH_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 },
- { PCH_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 },
- { PCH_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 },
+ { RP_DEV_PCIE1, 0x60, ELOG_WAKE_SOURCE_PME_PCIE1 },
+ { RP_DEV_PCIE2, 0x60, ELOG_WAKE_SOURCE_PME_PCIE2 },
+ { RP_DEV_PCIE3, 0x60, ELOG_WAKE_SOURCE_PME_PCIE3 },
+ { RP_DEV_PCIE4, 0x60, ELOG_WAKE_SOURCE_PME_PCIE4 },
+ { RP_DEV_PCIE5, 0x60, ELOG_WAKE_SOURCE_PME_PCIE5 },
+ { RP_DEV_PCIE6, 0x60, ELOG_WAKE_SOURCE_PME_PCIE6 },
+ { RP_DEV_PCIE7, 0x60, ELOG_WAKE_SOURCE_PME_PCIE7 },
+ { RP_DEV_PCIE8, 0x60, ELOG_WAKE_SOURCE_PME_PCIE8 },
+ { RP_DEV_PCIE9, 0x60, ELOG_WAKE_SOURCE_PME_PCIE9 },
+ { RP_DEV_PCIE10, 0x60, ELOG_WAKE_SOURCE_PME_PCIE10 },
+ { RP_DEV_PCIE11, 0x60, ELOG_WAKE_SOURCE_PME_PCIE11 },
+ { RP_DEV_PCIE12, 0x60, ELOG_WAKE_SOURCE_PME_PCIE12 },
+ { RP_DEV_PCIE13, 0x60, ELOG_WAKE_SOURCE_PME_PCIE13 },
+ { RP_DEV_PCIE14, 0x60, ELOG_WAKE_SOURCE_PME_PCIE14 },
+ { RP_DEV_PCIE15, 0x60, ELOG_WAKE_SOURCE_PME_PCIE15 },
+ { RP_DEV_PCIE16, 0x60, ELOG_WAKE_SOURCE_PME_PCIE16 },
+ { RP_DEV_PCIE17, 0x60, ELOG_WAKE_SOURCE_PME_PCIE17 },
+ { RP_DEV_PCIE18, 0x60, ELOG_WAKE_SOURCE_PME_PCIE18 },
+ { RP_DEV_PCIE19, 0x60, ELOG_WAKE_SOURCE_PME_PCIE19 },
+ { RP_DEV_PCIE20, 0x60, ELOG_WAKE_SOURCE_PME_PCIE20 },
+ { RP_DEV_PCIE21, 0x60, ELOG_WAKE_SOURCE_PME_PCIE21 },
+ { RP_DEV_PCIE22, 0x60, ELOG_WAKE_SOURCE_PME_PCIE22 },
+ { RP_DEV_PCIE23, 0x60, ELOG_WAKE_SOURCE_PME_PCIE23 },
+ { RP_DEV_PCIE24, 0x60, ELOG_WAKE_SOURCE_PME_PCIE24 },
};
maxports = MIN(CONFIG_MAX_ROOT_PORTS, ARRAY_SIZE(pme_status_info));
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